Team: Vivian Darkbloom Can Cede
Team member: Nathan Kitchen
UC Berkeley
Bio: Nathan Kitchen is a PhD student in the EECS Department at UC
Berkeley. He is currently working on constrained random verification
with Andreas Kuehlmann. He has a BS in EE from Brigham Young
University.
Team member: Donald Chai
UC Berkeley
Bio: Donald Chai hails from Brooklyn in New York City, meaning he
properly pronounces phrases such as "orange", "Super Mario Brothers",
and "forget about it". After being imbued with super EE and CS powers at
Cornell University, he decided to take up surfing and somehow ended up
in Berkeley, on the wrong end of California. There, he probes the deep
mysteries of design automation under the watchful (and infinitely
patient) eye of Andreas Kuehlmann. He received his MS degree and will
get his PhD in 2008.
Team number: 01
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Team: LaDS_Taiwan
Team member: Chih-Yuan Huang
National Taiwan University
Bio: Chih-Yuan Huang is a Ph. D candidate at the Graduate Institute of
Electronics Engineering, National Taiwan University. His major is
testing of digital circuits. His current focus is on fault-tolerant
circuit design and low-power testing techniques.
Team member: Tsung-Hsiu Ko
National Taiwan University
Bio: Tsung-Hsiu Ko is a graduate student in National Taiwan University
Electrical Engineering. His major is testing-related techniques and his
recent research focuses on fault tolerant circuit design.
Team number: 02
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Team: EECS228
Team member: I-Sheng Lin
National Tsing Hua University
Bio: I-Sheng majored in computer science and graduated from the National
Tsing Hua University in 2006. He is now a graduate student at NTHU
and his research interests include physical design automation, especially
placement and routing.
Team member: Che-Yu Liu
National Tsing Hua University
Bio: Che-Yu is a is a graduate student of National Tsing Hua University.
He is interested in Physical Design. His current focus is on global
routing in multiple layers.
Team number: 03
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Team: Bogo
Team member: Zhe-Wei Jiang
National Taiwan University
Bio: Zhe-Wei Jiang received the B.S. in Electronics Engineering from
National Chiao-Tung University, Taiwan, R.O.C., in 2003, and is currently
working toward the Ph.D. degree at National Taiwan University. His research
interests include VLSI placement.
Team member: Tung-Chieh Chen
National Taiwan University
Bio: Tung-Chieh Chen received the B.S. in Electrical Engineering from
National Taiwan University, Taiwan, R.O.C., in 2003, and is currently
working toward the Ph.D. degree at the same university. His research
interests include VLSI floorplanning and placement.
Team number: 04
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Team: CADgopher
Team member: Zhichun Wang
University of Minnesota
Bio: Zhichun is currently a phD candidate in the Electrical & Computer
Engineering Department at University of Minnesota, Twin Cities. He
graduated with a B.S. degree in Electrical Engineering from Tsinghua
University in China. He has worked on several projects about nonlinear
RF circuit macromodelling and two papers have been published at DAC2007
and CICC2007 respectively.
Team member: Chenjie Gu
University of Minnesota
Bio: Chenjie Gu is a PhD candidate in the Electrical & Computer
Engineering Department at the University of Minnesota, Twin Cities. He
received a BS degree in Electrical Engineering from Shanghai Jiao Tong
University. His current research interests include RF circuit
simulation and macromodelling, and applied numerical methods.
Team number: 05
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Team: Excelsior
Team member: Huang-Yu Chen
National Taiwan University
Bio: Huang-Yu Chen is working toward the Ph.D. degree in Graduate Institute of
Electronics Engineering at the National Taiwan University, Taipei, Taiwan.
He received his B.S. in electrical engineering from National Tsing Hua
University, Hsinchu, Taiwan, in 2004. His research interests are in
combinatorial optimization with applications to the VLSI design automation,
manufacturability-driven large-scale routing, and design for
manufacturability/reliability. He has two papers in the top conferences
(DAC, ICCAD), one paper in the top journal (TCAD), and two book chapters
published since 2006. He has received the 2006 Outstanding Research Award
from National Taiwan University and the Best Paper Nomination from
ICCAD-2007.
Team member: Chin-Hsiung Hsu
National Taiwan University
Bio: Chin-Hsiung Hsu is working toward the Ph.D. degree in Graduate
Institute of Electronics Engineering at the National Taiwan University,
Taipei, Taiwan. He received his B.S. in computer science and information
engineering from National Taiwan University, Taipei, Taiwan, in 2005.
His research interests are in combinatorial optimization with
applications to the VLSI design automation, large-scale global routing
and flip-chip design. He has three papers and one of these papers is
published in the top conference (DAC). He has received the 1st Prize,
IC/CAD Contest, Ministry of Education, Taiwan, 2005, 2007, and a Best
Paper Nomination from DAC-2007.
Team number: 06
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Team: The Bug Makers
Team member: Gustavo Wilke
Universidade Federal do Rio Grande do Sul (UFRGS)
Bio: Gustavo Wilke received his BS degree in Computer Engineering at
UFRGS in 2004. He started his PhD in 2005 at the same university under
the advisement of Prof. Ricardo Reis. From 2004 to 2005 for 6 months and
again from 2006 to 2007 for one year Gustavo has interned at Fujitsu
Laboratories of America. His research topic is clock distribution
architectures focusing on optimization of mesh-based architectures.
Team member: Cristiano Lazzari
Universidade Federal do Rio Grande do Sul (UFRGS)
Bio: Cristiano Lazzari is a PhD student at UFRGS working with algorithms
for automatic layout generation and fault-tolerant techniques. He
received his Master degree in Computer Science at UFRGS in 2003. His
research interests include physical design such as algorithms for layout
generation and timing analysis.
Team number: 07
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Team: Wahoos
Team member: Jiawei Huang
University of Virginia
Bio: Jiawei Huang is currently a Ph.D. student in the Computer
Engineering program at the University of Virginia. He received his
bachelor's degree in Electrical Engineering from Shanghai Jiao Tong
University in 2006, with a minor in Finance. His primary research
interest is design space exploration for algorithm/implementation
co-optimization. His favorite sport is soccer, but he enjoys all sports.
He hopes to travel around the world some day.
Team member: Michael Boyer
University of Virginia
Bio: Michael Boyer is currently a Ph.D. student in the Computer
Engineering program at the University of Virginia. He received his B.S.
in Computer Engineering from Union College in 2006, with a minor in
Math. His research focuses on techniques that allow multi-core
architectures to make run-time tradeoffs between throughput and latency.
Outside of academia, he enjoys playing rugby, soccer, and disc golf.
Team number: 08
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Team: Unsatisfiable
Team member: Tobias Welp
UC Berkeley
Bio: Tobias graduated in 2007 from Darmstadt University of Technology in
Germany. Now he is in his first year as a PhD student at the University
of California at Berkeley. His research interests are in logic synthesis
and formal verification.
Team member: Aaron Hurst
UC Berkeley
Bio: Aaron received his BS and MS from Carnegie Mellon University in
2002 and is current pursuing a Ph.D at the University of California,
Berkeley. He is part of the logic synthesis and verification group and
studies under Professor Robert Brayton. His research interests include
sequential optimization, design for yield, low power, and the
interaction between logic and physical synthesis. Aaron has just
finished his fifth year of studies and plans to graduate in a few delta
time steps.
Team number: 09
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Team: Timmy Star
Team member: Shang-Feng Chao
National Taiwan University
Bio: Shang-Feng Chao was born in Tainan City, Taiwan (R.O.C.) in 1984.
He received his B.S. degree in Electrical Engineering department in
National Taiwan University in Tapei, Taiwan in 2006. He is pursuing his
M.S. degree in Graduate Institute of Electronics Engineering in National
Taiwan University since September 2006. His research interests include
diagnosis on sequential circuits and delay fault tests.
Team member: Hsiu-Ting Lin
National Taiwan University
Bio: Hsiu-Ting Lin was born in Changhua County, Taiwan (R.O.C.) in 1984.
He received his B.S. degree in Electrical Engineering department in
National Taiwan University in Tapei, Taiwan in 2006. He is pursuing his
M.S. degree in Graduate Institute of Electronics Engineering in National
Taiwan University since September 2006. His research interests include
ATPG algorithm, low power testing and delay fault test.
Team number: 10
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Team: Model Checkers
Team member: Gaurav Vaidya
Penn State
Bio: Gaurav Vaidya is currently in his Master's in Electrical
Engineering program at the Pennsylvania State University. He graduated
in 2006 from the University of Mumbai, India, specializing in
Electronics Engineering. Along with VLSI design, he is quite interested
in the field of Computer Vision as well. He has currently decided to
explore the area of VLSI design verification as part of his thesis
research.
Team member: Zhiyang Ong
University of Southern California
Bio: Zhiyang Ong is a Masters student in the Ming Hsieh Department of
Electrical Engineering at the University of Southern California. He
received a B.E. degree with honors in Electrical and Electronics
Engineering from the University of Adelaide in 2005. His areas of
research interests include vertical profiling, test automation, and
physical design. He is currently working on parameterized statistical
model for vertical profiling of computer system performance.
Team number: 11
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Team: nthucs227
Team member: Ang-Chih Hsieh
National Tsing Hua University
Bio: Ang-Chih Hsieh received the B.S. degree in Computer Science from
National Tsing Hua University, Taiwan, in 2005. Currently he is working
toward the Ph.D. degree. His research interests include VLSI/CAD for low
power and high performance issues.
Team member: Chieh-Chun Chang
National Tsing Hua University
Bio: Chieh-Chun Chang is a second year graduate student at the National
Tsing Hua University in Taiwan. His advisor is Prof. TingTing Hwang. His
current research is on thermal sensors and future research is focused
on multiple thermal issues.
Team number: 12
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Team: BuZZCaD
Team member: Mohit Pathak
Georgia Institute of Technology
Bio: Mohit is a PhD student at School of ECE , Georgia Insitute of
Technology. His research interests include CAD for VLSI, physical design
automation and RF circuits layout generation. He received his BTech in
Computer Science and Engineering from Indian Institute of Technology
Kharagpur in 2004.
Team member: Dae Hyun Kim
Georgia Institute of Technology
Bio: Dae Hyun Kim is a PhD student at Georgia Institute of Technology.
His research interests involve physical design automation algorithms. He
received the BS degree in EE from Seoul National University in Korea,
and the MS degree in ECE from Georgia Institute of Technology.
Team number: 13
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Team: UTDA
Team member: Anurag Kumar
UT Austin
Bio: Anurag is a first year PhD student at University of Texas at Austin.
He received his B.Tech from IIT Kharagpur in 2006. He was working at
Atrenta from 2006-07 on Clock domain Crossing product. His current
research interests are in Physical Design Automation.
Team member: Ashutosh Chakraborty
UT Austin
Bio: Ashutosh Chakraborty received the BTech degree in Electrical
Engineering from the Indian Institute of Technology, New Delhi, India in
2002. He worked as Senior Member Technical Staff at Mentor Graphics
India (2002-2004) and as Research Assistant at Politecnico di Torino,
Italy (2004-2006). He is currently at University of Texas, Austin, USA
as a PhD Student in the department of Electrical and Computer
Engineering where his research focus is on Physical Design Algorithms
for Manufacturability. Ashutosh is a student member of the IEEE.
Team number: 14
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Team: Newcastle United
Team member: Andrey Mokhov
Newcastle University
Bio: Andrey Mokhov is a third year PhD student in School of EECE,
University of Newcastle, UK. He is doing research in the area of
asynchronous systems modelling, synthesis and verification. His current
projects are high-level models verification based on unfoldings theory
and efficient specification and synthesis of large asynchronous
controllers based on conditional partial orders.
Team member: Yu Zhou
Newcastle University
Bio: Yu Zhou is a final year PhD student in School of EECE, University
of Newcastle, UK. His PhD thesis is on synthesis and optimization of
asynchronous data paths. His research interests include logic synthesis
and verification, asynchronous design automation and low power design
techniques.
Team number: 15
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Team: Cadators
Team member: Mihir Choudhury
Rice University
Bio: Mihir Choudhury is a third year Phd student in ECE department at
Rice university. His research interests include logic design for
reliability and theoretical bounds on computation in the presence of
noise.
Team member: Kai Sun
Rice University
Bio: Kai Sun received a Bachelor degree (2000) from Peking University
and a Master degree (2003) from Chinese Academy of Sciences. He is
expecting his Ph.D. from Department of Computational & Applied
Mathematics (CAAM) of Rice University at Houston, Texas early next year.
Mr. Sun is interested in general area of scientific computing. He
currently works with Dr. Sorensen in domain decomposition and dimension
reduction techniques for dynamical systems. Previously, he worked on
numerical optimization problems with Dr. Yuan. He also served as intern
for several companies including Microsoft Research, BP and Spectrum
Prime.
Team number: 16
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Team: A & T
Team member: Szu-Yu Chen
National Taiwan University
Bio: Szu-Yu Chen received the B.S. degree in electrical engineering from
the National Taiwan University, Taiwan, R.O.C., in 2007. He is
currently working toward the M.S. degree at the Graduate Institute of
Electronics Engineering, National Taiwan University, Taiwan, R.O.C.
His current research interests include VLSI electronic design
automation, large-scale routing, and design for
manufacturability/reliability.
Team member: Ruey-Shi Rau
National Taiwan University
Bio: Ruey-Shi Rau is a Master student in the Graduate Institute of
Electronics Engineering at the National Taiwan University. He received
his B.S. degree in Electrical Engineering from National Taiwan
University in 2007. His research focuses on formal verification.
Team number: 17
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Team: Minke
Team member: Chi-An Wu
National Taiwan University
Bio: Chi-An Wu received the B.S. in Electrical Engineering from National
Taiwan University, Taiwan, in 2005, and is currently working toward the
M.S. degree at the same university. His current research topic focuses
on hardware verification.
Team member: Kai-Fu Tang
National Taiwan University
Bio: Kai-Fu Tang is a Ph.D. student in National Taiwan University. His
current research topic focuses on software verification.
Team number: 18
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Team: Utes
Team member: Christopher Condrat
University of Utah
Bio: Christopher Condrat is a graduate student in Electrical Engineering
at the University of Utah. He recently completed his Masters Degree and
is now pursing a PhD, researching synthesis techniques for optical gate
logic.
Team member: Sivaram Gopalakrishnan
University of Utah
Bio: Sivaram Gopalakrishnan is a PhD student in the Department of
Electrical and Computer Engineering at the University of Utah. He has
completed his Masters in Electrical Engineering from the University of
Utah and Bachelors in Electronics and Communication Engineering from
University of Madras, India. Currently for his Ph.D. program, he is
working towards high level synthesis of arithmetic datapaths.
Team number: 19
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