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Team: UnderdogsTeam member: Matthew GuthausAdvisor: Richard Brown and Dennis Sylvester University: University of Michigan Bio: Matthew is currently a Ph.D. Candidate in Electrical Engineering at the University of Michigan and expects to graduate near the beginning of the 2006 calendar year. His dissertation research is on design automation of robust clock networks using parametric statistical STA. Other research interests include physical design automation, low-power architecture for embedded systems, and algorithm specific microprocessors.
Team member: Jarrod Roy
Team number: 1
Team: MinnCadTeam member: Jaskirat SinghAdvisor: Sachin Sapatnekar University: Univeristy of Minnesota Bio: My research interests are design and analysis of power/ground networks, statistical timing analysis and statistical circuit optimization.
Team member: Pongstorn Maidee
Team number: 2
Team: ChurrasCADaTeam member: Gustavo NeubergerAdvisor: Ricardo Reis University: Federal University of Rio Grande do Sul (UFRGS) Bio: Gustavo is a PhD student at UFRGS working with design and automatic generation of fault-tolerant circuits, and effects of process variability in integrated circuits. He received his BS degree in Computer Engineering at UFRGS in 2003. His research interests include physical design, design of fault tolerant circuits, design for manufacturability and process variability.
Team member: Renato Hentschke
Team number: 3
Team: CAD-buryTeam member: Siddharth GargAdvisor: Diana Marculescu University: Carnegie Mellon Bio: Siddharth is first year Phd. student in the Electrical and Computer Engineering Dept. at Carnegie Mellon University. His research interests include low power VLSI deign and energy aware computing.
Team member: Puru Choudhary
Team number: 4
Team: EDA@NTUTeam member: Tai-Chen ChenAdvisor: Yao-Wen Chang University: National Taiwan University Bio: Tai-Chen is a Ph.D. candidate in the Graduate Institute of Electronics Engineering at the National Taiwan University. His research interests include VLSI design automation, architectures, and systems (with emphasis on physical design for nanometer IC technologies and SoC integration) and combinatorial optimization. His current research topic focuses on gridless routing considering nanometer electrical effects.
Team member: Jia-Wei Fang
Team number: 5
Team: NTUathlonTeam member: Tung-Chieh ChenAdvisor: Yao-Wen Chang University: National Taiwan University Bio: Tung-Chieh Chen received the B.S. in Electrical Engineering from National Taiwan University, Taiwan, R.O.C., in 2003, and is currently working toward the Ph.D. degree at the same university. His research interests include VLSI floorplanning and placement.
Team member: Chih-Yuan Huang
Team number: 6
Team: Circuit BreakersTeam member: Nirav DaveAdvisor: Arvind University: MIT Bio: Nirav is a 3rd-year graduate student working in high-level synthesis and computer architecture. In his spare time, Nirav enjoys cycling, most manner of card games, and referring to himself in the third person.
Team member: Michael Pellauer
Team number: 7
Team: ChimasCADTeam member: Gustavo Reis WilkeAdvisor: Ricardo Augosto da Luz Reis University: UFRGS Bio: Gustavo works in the timing analysis and clock distribution area. He is also interested in statistical timing analysis and yield prediction. He has been working on CAD since 2001 as an undergraduate research assistant.
Team member: Lucas Brusamarello
Team number: 8
Team: MSCADTeam member: Jeffrey FanAdvisor: Sheldon Tan University: University of California, Riverside Bio: Jeffrey Fan is currently a PhD student in University of California, Riverside. He brings in more than ten years of working experience in the industry before joining UCR. His interest of research includes VLSI simulation, modeling, and power/ground optimization. Prior to his study, Jeffrey served as Vice President of Vivavr Technology, Inc., and General Manager/co-founder of Musica Technologies, Inc. From 1988 to 2002, he held various senior technical positions in Western Digital, Emulex Corporation, Adaptec Inc., and Toshiba America. Jeffrey received his M.S. degree in electrical engineering from State University of New York at Buffalo. He also holds BSEE degree from National Chiao Tung University in Taiwan.
Team member: Pu Liu
Team number: 9
Team: CADMinnatorsTeam member: Sanjay KumarAdvisor: Sachin Sapatnekar University: Univ of Minnesota Bio: Sanjay Kumar obtained his Bachelors of Engineering (Electrical and Electronics) from BITS-Pilani, India. He is working towards a PhD degree in the Department of Electrical Engineering at the University of Minnesota. His research interests include variability aware CAD techniques for present day digital circuits.
Team member: Nitin Nagarkatte
Team number: 10
Team: SU OrangeTeam member: Divya MullasseryAdvisor: Nazanin Mansouri University: Syracuse University Bio: Divya Mullassery is a second year graduate student in the Department of Electrical Engineering and Computer Science at Syracuse University. She completed her B.Tech in Electrical and Electronics Engineering from Regional Engineering College Calicut, India in 2002. She worked as Design Engineer(R&D) at BPL Telecom in the field of Microcontroller based System Design from 2002 till 2004. Her research interests include development of CAD tools for System Level and Physical Design.
Team member: Priyank Parakh
Team number: 11
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