Sponsored by SIGDA
SIGDA Contact
Prof. Nikil Dutt
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Problems and References
To download the tar.gz file for all related papers, click here.
To download the problem descriptions and give-away source code, click here.
Problem 1: Analysis & Circuit Design
Contributed by: Frank Liu, IBM Research
Overview:
The problem is about
static timing analysis of a combinational circuit with the critical path
method.
"Timing analysis for combinational circuits",
Chapter 5, from "Timing" by Sachin Sapatnekar,
Kluwer Academic Publishers, 2004
Problem 2: Physical Design
Contributed by: Jiang Hu, Texas A&M University
Overview:
The problem is concerned with
simultaneous buffer insertion and Steiner tree adjustment considering
buffer blockages.
"Buffer Insertion With Adaptive Blockage Avoidance",
Jiang Hu, Charles J. Alpert, Stephen T. Quay, and Gopal Gandham,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 22, No. 4, April 2003, pp. 492-498
Problem 3: Logic & High-Level Synthesis
Contributed by: Geert Janssen, IBM Research
Overview:
Implement a certain normalization of logic expressions.
No dedicated paper.
Any introductory course to logic synthesis will suffice, e.g.
S. Devadas, A. Ghosh, K. Keutzer, Logic Synthesis, McGraw-Hill, 1994, or
G. DeMicheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill,
1994.
Problem 4: System Design and Analysis
Contributed by: Matteo Frigo, IBM Research
Overview:
This problem asks for the
design of linear-phase FIR filters via linear programming.
"Meteor: A Constrained-based FIR Filter Design Program",
K. Steiglitz, T.W. Parks, and J.F. Kaiser,
IEEE Trans. Signal Processing, Vol. 40, No. 8, August 1992, pp. 1901-1909
Problem 5: Functional Verification
Contributed by: Geert Janssen, IBM Research
Overview:
The title of the paper says it all! Oh, and you might want to
check up on equivalence relations.
"Detection of Equivalent State Variables in Finite State Machine
Verification",
C.A.J. van Eijk, and J.A.G. Jess,
Workshop notes of the 1995 IWLS,
1995, pp. 3.35-3.44
Problem 6: Timing, Test, and Manufacturing
Contributed by: Kedarnath Balakrishnan, NEC Labs America
Overview:
This problem motivates the use of multiple detection test patterns to improve
manufacturing test quality.
"Impact of Multiple-Detect Test Patterns on Product Quality",
Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge,
Prabhu Krishnamurthy Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski,
Proceedings of the International Test Conference,
2003, pp. 1031-1040
Computer Platform
During the contest one desktop computer will be available per team.
This will be a Pentium III running SuSE 9.1 Linux. All necessary software and
the problem statements will be pre-installed. Also, in your home directory you
will find a recommended directory structure to organize your work.
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