This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is OSCI SystemC 2.2.0. All of the hardware modules satisfies the OSCI standards.

The simulator is composed of a CPU, cache, and memory components including DDR SDRAM, MLC NOR Flash, MLC NAND Flash, SRAM. Each memory components have it’s own memory model, which enables cycle-accurate power consumption estimation of the devices. Master and slave SystemC IPs are connected through AMBA AHB CLI (Cycle-Level Interface). You will get energy trace files for each memory devices. You will get cycle-accurate performance evaluation results CPU cycle counts information, and cache hit/miss ratio on console. Also, you can get trace files for memory devices.

The simulator exhibits performance over 500 K instructions / sec, which is fairly high for a cycle-accurate system-level simulator.

The simulator’s source code is fully open to public. So anyone can use it and modify it at one’s will. However, we strongly recommend users to contact the developers to upgrade and maintain the simulator.

You can download the simulator from the following link.

[LINK]