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Total: 99
K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," in Proceedings of the IEEE, vol. 91, no. 2, IEEE, 0018-9219, pp.305-327, February, 2003. [IEEExplorer]
K. S. Khouri and N. K. Jha, "Leakage power analysis and reduction during behavioral synthesis," in IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, IEEE Computer Society, 0-7695-0801-4, pp.876-885, December, 2002. [IEEExplorer][ACM Portal]
S. M Martin, K. Flautner, T. Mudge, D., "Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Lower Power Microprocessors under Dynamic Workloads," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD-02), ACM, 1092-3152, pp.721-725, New York, USA, November, 2002. [ACM Portal]
J. Kao, S. Narendra, and A. Chandrakasan, "Subthreshold leakage modeling and reduction techniques," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), ACM, 0-7803-7607-2, pp.141-148, San Jose, USA, November, 2002. [IEEExplorer][ACM Portal]
F. Hamzaoglu and M. R. Stan, "Circuit-level techniques to control gate leakage for sub- 100nm CMOS," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-5811-3475-4, pp.60-63, Monterey, USA, August, 2002. [IEEExplorer][ACM Portal]
C. H. Kim and K. Roy, "Dynamic vt SRAM: A leakage tolerant cache memory for low voltage microprocessors," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-475-4, pp.251-254, Monterey, USA, August, 2002. [ACM Portal]
M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, "Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique," in ACM/IEEE 39th Design Automation Conference (DAC-02), ACM, 1-58113-461-4, pp.480-485, New Orleans, USA, June, 2002. [IEEExplorer][ACM Portal]
A. Ferre and J. Figueras, "Leakage power bounds in CMOS digital technologies," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 0278-0070, pp.731-738, June, 2002. [IEEExplorer]
S. Sirichotiyakul, T. Edwards, C. Oh, R. Panda, and D. Blaauw, "Duet: An accurate leakage estimation and optimization tool for dual-vt circuits," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Educational Activities Department, 1063-8210, pp.79-90, April, 2002. [ACM Portal]
M. C. Johnson, D. Somasekhar, L.-Y. Chiou, and K. Roy, "Leakage control with efficient use of transistor stacks in single threshold CMOS," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ACM, 1-58133-109-7, pp.1-5, February, 2002. [ACM Portal]
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