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Total: 99
B. Chatterjee, M. Sachdev, S. Hsu, R. Krishnamurthy, and S. Borkar, "Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-682-X, pp.122-127, Seoul, Korea, August, 2003. [IEEExplorer][ACM Portal]
N. Jayakumar and S. P. Khatri, "An ASIC design methodology with predictably low leakage, using leakage-immune standard cells," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-682-X, pp.128-133, Seoul, Korea, August, 2003. [IEEExplorer][ACM Portal]
C. H. Kim, J.-J. Kim, S. Mukhopadhyay, and K. Roy, "A forward body-biased low-leakage SRAM cache: device and architecture considerations," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-682-X, pp.6-9, Seoul, Korea, August, 2003. [IEEExplorer][ACM Portal]
S. Mukhopadhyay, C. Neau, R. T. Cakici, A. Agarwal, C. H. Kim, and K. Roy, "Gate leakage reduction for scaled devices using transistor stacking," in IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, IEEE Educational Activities Department, 1063-8210, pp.716-730, August, 2003. [IEEExplorer][ACM Portal]
C. Neau and K. Roy, "Optimal body bias selection for leakage improvement and process compensation over different technology generations," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-682-X, pp.116-121, Seoul, Korea, August, 2003. [IEEExplorer][ACM Portal]
R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, "Statistical estimation of leakage current considering inter- and intra-die process variation," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-682-X, pp.84-89, Seoul, Korea, August, 2003. [IEEExplorer][ACM Portal]
R. M. Rao, J. L. Burns, A. Devgan, and R. B. Brown, "Efficient techniques for gate leakage estimation," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-682-X, pp.100-103, Seoul, Korea, August, 2003. [IEEExplorer][ACM Portal]
A. Srivastava, "Simultaneous vt selection and assignment for leakage optimization," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-682-X, pp.146-151, Seoul, Korea, August, 2003. [IEEExplorer][ACM Portal]
D. Lee and D. Blaauw, "Static leakage reduction through simultaneouos threshold voltage and state assignment," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM, 1-58113-688-9, pp.191-194, Anaheim, USA, June, 2003. [IEEExplorer][ACM Portal]
R. S. Guindi and F. N. Najm, "Design Techniques for Gate-Leakage Reduction in CMOS Circuits," in IEEE International Symposium on Quality Electronic Design (ISQED), IEEE Computer Society, 0-7695-1881-8, pp.61-65, washington DC, USA, March, 2003. [ACM Portal]
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