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Total: 99
N. Hanchate and N. Ranganathan, "LECTOR: a technique for leakage reduction in CMOS circuits," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1063-8210, pp.196-205, February, 2004. [IEEExplorer]
N.-S. Kim, K. Flautner, D. Blaauw, and T. Mudge, "Circuit and microarchitectural techniques for reducing cache leakage power," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Educational Activities Department, 1063-8210, pp.167-184, February, 2004. [IEEExplorer][ACM Portal]
D. Lee, D. Blaauw, and D. Sylvester, "Gate oxide leakage current analysis and reduction for VLSI circuits," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Educational Activities Department, 1063-8210, pp.155-166, February, 2004. [IEEExplorer][ACM Portal]
A. Rahman and V. Polavarapuv, "Evaluation of low-leakage design techniques for field-programmable gate arrays," in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, ACM, 1-58113-829-6, pp.23-30, Monterey, USA, February, 2004. [ACM Portal]
N.S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J.S. Hu, M.J. Irwin, M. Kandemir, V. Narayanan, "," in IEEE Computer, Vol 36, No. 12, IEEE Computer Society, 0018-9162, pp.68-75, December, 2003.
N.S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J.S. Hu, M.J. Irwin, M. Kandemir, V. Narayanan, "Leakage current: Moore's law meets static power," in IEEE Computer, Vol 36, No. 12, IEEE Computer Society, 0018-9162, pp.68-75, December, 2003.
R. M. Rao, F. Liu, J. L. Burns, and R. B. Brown, "A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), IEEE Computer Society, 1-58113-762-1, pp.689-692, San Jose, USA, November, 2003. [IEEExplorer][ACM Portal]
T. Chen and S. Naffziger, "Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation," in IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, IEEE Educational Activities Department, 1063-8210, pp.888-889, October, 2003. [IEEExplorer][ACM Portal]
N. Azizi, F. N. Najm, and A. Moshovos, "Low-leakage asymmetric-cell SRAM," in IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, IEEE Educational Activities Department, 1-5811-3475-4, pp.701-715, August, 2003. [IEEExplorer][ACM Portal]
B. H. Calhoun, F. A. Honore, and A. Chandrakasan, "Design methodology for fine-grained leakage control in MTCMOS," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-682-X, pp.104-109, Seoul, Korea, August, 2003. [IEEExplorer][ACM Portal]
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