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Total: 99
S. Mukhopadhyay, A. Raychowdhury, and K. Roy, "Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 0278-0070, pp.363-381, March, 2005. [IEEExplorer]
P. Babighian, L. Benini, A. Macii, and E. Macii, "Post-layout leakage power minimization based on distributed sleep transistor insertion," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-929-2, pp.138-143, Newport Beach, USA, August, 2004. [ACM Portal]
R. Rao, A. Agarwal, D. Sylvester, R. Brown, K. Nowka, and S. Nassif, "Approaches to run-time and standby mode leakage reduction in global buses," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-929-2, pp.188-193, Newport Beach, USA, August, 2004. [IEEExplorer][ACM Portal]
A. Agarwal, C.-H. Kim, S. Mukhopadhyay, K. Roy, "Leakage in nano-scale technologies: mechanisms, impact and design considerations," in ACM/IEEE 41st Design Automation Conference (DAC-04), ACM, 1-58113-828-8, pp.6-11, San Diego, USA, June, 2004. [ACM Portal]
A. Basu, S.-C. Lin, V. Wason, A. Mehrotra, and K. Banerjee, "Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era," in ACM/IEEE 41st Design Automation Conference (DAC-04), ACM, 1-51183-828-8, pp.884-887, San Diego, USA, June, 2004. [IEEExplorer][ACM Portal]
H. S. Deogun, R. R. Rao, D. Sylvester, and D. Blaauw, "Leakage- and crosstalk-aware bus encoding for total power reduction," in ACM/IEEE 41st Design Automation Conference (DAC-04), ACM, 1-58113-828-8, pp.779-782, San Diego, USA, June, 2004. [IEEExplorer][ACM Portal]
L. He, W. Liao, and M. R. Stan, "System level leakage reduction considering the interdependence of temperature and leakage," in ACM/IEEE 41st Design Automation Conference (DAC-04), ACM, 1-51183-828-8, pp.12-17, San Diego, USA, June, 2004. [IEEExplorer][ACM Portal]
R. Jejurikar, C. Pereira, and R. Gupta, "Leakage aware dynamic voltage scaling for real-time embedded systems," in ACM/IEEE 41st Design Automation Conference (DAC-04), ACM, 1-58113-828-8, pp.275-280, San Diego, USA, June, 2004. [IEEExplorer][ACM Portal]
V. Kursun and E. G. Friedman, "Sleep switch dual threshold voltage domino logic with reduced standby leakage current," in IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, IEEE Educational Activities Department, 1063-8210, pp.485-496, May, 2004. [IEEExplorer][ACM Portal]
A. Abdollahi, F. Fallah, and M. Pedram, "Leakage current reduction in CMOS VLSI circuits by input vector control," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1063-8210, pp.140-154, Los Angeles, USA, February, 2004. [IEEExplorer]
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