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Total: 99
M.-L. Mui, K. Banerjee, and A. Mehrotra, "Supply and power optimization in leakage-dominant technologies," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 0278-0070, pp.1362-1371, September, 2005. [IEEExplorer]
H. Hassan, M. Anis, and M. Elmasry, "LAP: a logic activity packing methodology for leakage power-tolerant FPGAs," in ACM/IEEE International Symposium on Low Power Electronics and Design, 1-59593-137-6, pp.257-262, San Diego, USA, August, 2005. [IEEExplorer]
M. Sumita, "High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-59593-137-6, pp.203-208, San Diego, USA, August, 2005. [IEEExplorer][ACM Portal]
D. Lee, D. Blaauw, and D. Sylvester, "Static leakage reduction through simultaneous vt/tox and state assignment," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 0278-0070, pp.1014-1029, July, 2005. [IEEExplorer]
S. Bhunia, N. Banerjee, Q. Chen, H. Mahmoodi, and K. Roy, "A novel synthesis approach for active leakage power reduction using dynamic supply gating," in ACM/IEEE 42nd Design Automation Conference (DAC-05), ACM, 1-59593-058-2, pp.479-484, Anaheim, USA, June, 2005. [IEEExplorer][ACM Portal]
H. Chang and S. S. Sapatnekar, "Full-chip analysis of leakage power under process variations, including spatial correlations," in ACM/IEEE 42nd Design Automation Conference (DAC-05), ACM, 1-59593-058-2, pp.523-528, Anaheim, USA, June, 2005. [IEEExplorer][ACM Portal]
N. Jayakumar, S. Dhar, and S. P. Khatri, "A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents," in ACM/IEEE 42nd Design Automation Conference (DAC-05), ACM, 1-59593-058-2, pp.43-46, Anaheim, USA, June, 2005. [IEEExplorer][ACM Portal]
X. Tang, H. Zhou, and P. Banerjee, "Leakage power optimization with dual-vth library in high-level synthesis," in ACM/IEEE 42nd Design Automation Conference (DAC-05), ACM, pp.202-207, Anaheim, USA, June, 2005. [ACM Portal]
V. Khandelwal, A. Davoodi, and A. Srivastava, "Simultaneous vt selection and assignment for leakage optimization," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1063-8210, pp.762-765, June, 2005. [IEEExplorer]
C. H.-I. Kim, J.-J. Kim, S. Mukhopadhyay, and K. Roy, "A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1063-8210, pp.349-357, March, 2005. [IEEExplorer]
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