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Total: 99
K. Patel, L. Benini, E. Macii, and M. Poncino, "STVCache: A Leakage Energy-Efficient Architecture for Data Caches," in 17th ACM Great Lakes Symposium on VLSI, ACM, 1-59593-347-6, pp.404-409, Philadelphia, USA, April, 2006. [ACM Portal]
J. H. Anderson and F. N. Najm, "Active leakage power optimization for FPGAs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM, 1-58113-829-6, pp.423-437, March, 2006. [IEEExplorer][ACM Portal]
I. A. Ferzli and F. N. Najm, "Analysis and verification of power grids considering process-induced leakage-current variations," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 0278-0070, pp.126-143, January, 2006. [IEEExplorer]
G. Yang, Z. Wang and S.-M. Kang, "Gate leakage tolerant circuits in deep sub-100 nm CMOS technologies," in Smart Materials and Structures, Vol. 15, INSTITUTE OF PHYSICS, 0964-1726, pp.0-0, Santa Cruz, USA, December, 2005. [Link#1]
A. K. Sultania, D. Sylvester, and S. S. Sapatnekar, "Gate oxide leakage and delay tradeoffs for dual-tox circuits," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1063-8210, pp.1362-1375, December, 2005. [IEEExplorer]
W. Liao, J. M. Basile, and L. He, "Microarchitecture-level leakage reduction with data retention," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Educational Activities Department, 1063-8210, pp.1324-1328, November, 2005. [IEEExplorer][ACM Portal]
A. Raychowdhury, B. C. Paul, S. Bhunia, and K. Roy, "Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Educational Activities Department, 1063-8210, pp.1213-1224, November, 2005. [IEEExplorer][ACM Portal]
S. Kaxiras, P. Xekalakis, and G. Keramidas, "A simple mechanism to adapt leakage-control policies to temperature," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-59593-137-6, pp.54-59, San Diego, USA, October, 2005. [IEEExplorer][ACM Portal]
N.-S. Kim, D. Blaauw, and T. Mudge, "Quantitative analysis and optimization techniques for on-chip cache leakage power," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1063-8210, pp.1147-1156, October, 2005. [IEEExplorer]
N. Azizi and F. N. Najm, "Look-up table leakage reductions for FPGAs," in IEEE Custom Integrated Circuits Conference (CICC), 0-7803-9023-7, pp.187-190, San Jose, USA, September, 2005. [IEEExplorer]
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