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Total: 99
S. Mukhopadhyay, K. Kim, C.-T. Chuang, and K. Roy, "Modeling and analysis of leakage currents in double-gate technologies," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 0278-0070, pp.2052-2061, October, 2006. [IEEExplorer]
R. R. Rao, A. Devgan, D. Blaauw, and D. Sylvester, "Analytical yield prediction considering leakage/performance correlation," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 0278-0070, pp.1685-1695, September, 2006. [IEEExplorer]
P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, "Gate-length biasing for runtime-leakage control," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 0278-0070, pp.1475-1485, August, 2006. [IEEExplorer]
S. Mukhopadhyay, S. Bhunia, and K. Roy, "Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 0278-0070, pp.1486-1495, August, 2006. [IEEExplorer]
D.-S. Chiou, S.-H. Chen, S.-C. Chang, C. Yeh, "Timing driven power gating," in ACM/IEEE 43rd Design Automation Conference (DAC-06), ACM, 1-59593-381-6, pp.121-124, San Francisco, USA, July, 2006. [IEEExplorer][ACM Portal]
H.-O. Kim and Y. Shin, "Physical design methodology of power gating circuits for standard-cell-based design," in ACM/IEEE 43rd Design Automation Conference (DAC-06), ACM, 1-59593-381-6, pp.109-112, San Francisco, USA, July, 2006. [ACM Portal]
L. Cheng, L. Deng, D. Chen, and M. D.-F. Wong, "A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction," in ACM/IEEE 43rd Design Automation Conference (DAC-06), ACM, 1-59593-381-6, pp.117-120, San Francisco, USA, July, 2006. [IEEExplorer][ACM Portal]
Y. Meng, T. Sherwood, and R. Kastner, "Leakage power reduction of embedded memories on FPGAs through location assignment," in ACM/IEEE 43rd Design Automation Conference (DAC-06), ACM, 1-59593-381-6, pp.612-617, San Francisco, USA, July, 2006. [IEEExplorer][ACM Portal]
S. Shah, P. Gupta, and A. Kahng, "Standard cell library optimization for leakage reduction," in ACM/IEEE 43rd Design Automation Conference (DAC-06), ACM, 1-59593-381-6, pp.983-986, San Francisco, USA, July, 2006. [IEEExplorer][ACM Portal]
K.-S. Min, H.-D. Choi, H.-Y. Choi, H. Kawaguchi, and T. Sakurai, "Leaking-suppressed clock-gating circuit with zigzag super cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-v-vdd lsis," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Educational Activities Department, 1063-8210, pp.430-435, April, 2006. [ACM Portal]
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