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Total: 99
A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar, and V. De, "Effectiveness of referse body bias for leakage control in scaled dual vt CMOS ICs," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-371-5, pp.207-212, Huntington Beach, USA, August, 2001. [IEEExplorer][ACM Portal]
S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, "Scaling of stack effect and its application for leakage reduction," in ACM/IEEE International Symposium on Low Power Electronics and Design, ACM, 1-58113-371-5, pp.195-200, Huntington Beach, USA, August, 2001. [IEEExplorer][ACM Portal]
S. Kaxiras, H. Zhigang, M. Martonosi, "Cache decay: exploiting generational behavior to reduce cache leakage power," in 28th Annual International Symposium on Computer Architecture (ISCA-2001), ACM, 0163-5964, pp.240-251, New York, USA, May, 2001. [ACM Portal]
M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar, "Reducing leakage in a high-performance deep-submicron instruction cache," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Educational Activities Department, 1063-8210, pp.77-89, February, 2001. [IEEExplorer][ACM Portal]
A. Keshavarzi, K. Roy, and C. F. Hawkins, "Intrinsic leakage in deep submicron CMOS ICs - measurement-based test solutions," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Educational Activities Department, 1063-8210, pp.717-723, December, 2000. [ACM Portal]
M. C. Johnson, D. Somasekhar, and K. Roy, "Models and algorithms for bounds on leakage in CMOS circuits," in IEEE Transactions on Computer-Aided Design, 0278-0070, pp.714-725, June, 1999. [IEEExplorer]
S. Bobba and I. N. Hajj, "Maximum leakage power estimation for CMOS circuits," in IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 0-7695-0019-6, pp.116-124, Como, Italy, March, 1999. [IEEExplorer][ACM Portal]
Z. Chen, M. Johnson, L. Wei, and K. Roy, "Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks," in ACM/IEEE International Symposium on Low Power Electronics and Design, 1-58113-059-7, pp.239-244, Monterey, USA, August, 1998. [IEEExplorer][ACM Portal]
J. P. Halter and F. N. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," in IEEE 1997 Custom Integrated Circuits Conference, 0-7803-3669-0, pp.475-478, Santa Clara, USA, May, 1997. [IEEExplorer]
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