=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membership. Circulation: 2,700 =============================================================================== 1 January 2010 ACM/SIGDA E-NEWSLETTER Vol. 40, No. 1 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Soheil Ghiasi Contributing author: Matthew Guthaus Contributing author: Umit Y Ogras Contributing author: Marc Riedel Contributing author: Lin Yuan (2) "What is the statistical method for at-speed testing?" Contributing author: Dr. Jinjun Xiong, IBM From: Deming Chen (3) Paper Submission Deadlines From: Debjit Sinha (4) Upcoming Conferences and Symposia From: Debjit Sinha (5) Upcoming Funding Opportunities From: Qinru Qiu (6) Call for Papers ACM TECS Special Issue on Embedded Systems for Real-time Multimedia (ESTIMedia 2009) From: Naehyuck Chang (7) Call for Papers ACM TODAES Special Section on Low Power Electronics and Design From: Naehyuck Chang =============================================================================== Dear ACM/SIGDA members, Happy New Year! In this issue, we include a new article titled "What is the statistical method for at-speed testing?" contributed by Dr. Jinjun Xiong of IBM. We welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Qing Wu, E-Newsletter Editor; Matthew Guthaus, E-Newsletter Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Debjit Sinha, E-Newsletter Associate Editor; Lin Yuan, E-Newsletter Associate Editor; Soheil Ghiasi, E-Newsletter Associate Editor; Deming Chen, E-Newsletter Associate Editor; Umit Y Ogras, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "U.S. Awards $47 Million For R&D on IT Energy Savings" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=222200489 The Energy Department will fund 14 projects across the U.S. to develop technologies for improving energy efficiency in data centers and telecommunications networks. "Qualcomm to Jump From 45- to 28-nm with TSMC" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=222300029 Wireless technology company Qualcomm Inc. (San Diego, Calif.) has said it working with Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan) on 28-nm process technology and that it intends to move directly to the advanced process. Tape-outs on the 28-nm node are expected in mid-2010. "EU Project Readies UML/SysML-based HW/SW Codesign Tool" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=222200494 A first technology solution has emerged from the European Union's Framework7 SATURN project: a UML/SysML-based hardware/software co-design solution based on Artisan Studio, a modeling suite from Artisan Software Tools Ltd. (Cheltenham, England). "Nvidia Launches Tegra 2 Processor" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=222300041 Nvidia Corp. (Santa Clara, Calif.) has launched its ARM-based Tegra 2 processor. The device appears to be aimed at tablet computers but could also show the future direction for mainstream processors, which are expected to combine, as the Tegra 2 does, CPU, graphics and video functions. "Marvell Claims First Quad-Core ARM Processor" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=222200443 Marvell Technology Group Ltd., a supplier of chips for storage, communications and consumer electronics, claims to have developed the world's first "quadruple" core processor based on the ARM architecture. "Intel Demonstrates Moorestown Smartphones and Tablet Running Moblin, Including LG" http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3716 Moorestown is Intel's Atom based SoC that's designed for smartphones. The chip will be out in Q2 2010, with phones and devices available in the second half of 2010. Today Intel showed us three devices based on Moorestown, two phones and one tablet. "VIZIO Unveils Three New Portable TVs" http://www.dailytech.com/article.aspx?newsid=17341 One of the most important technologies at CES this year has turned out to be 3D-ready TVs and the corresponding 3D programming from major satellite providers. Another of the technologies that has been huge at the show has been portable TVs. "Motorola May Enter Tablet PC Market" http://www.dailytech.com/article.aspx?newsid=17326 Motorola will build future device for Google Motorola is struggling to revamp its mobile devices business in the face of increasing loses. Motorola is enjoying some success with the new Android powered smartphones that it is offering on the market. "Under the Lid: Analog Test is Suddenly the Critical Ingredient" http://www.edn.com/article/CA6713702.html ATPG (automatic-test-pattern generation), BIST (built-in self-test), and structural-test techniques have kept digital-test costs nearly constant during the explosion in digital complexity. Without these tools, however, as analog complexity starts to grow rapidly, analog-test cost is growing, too. "SIA Reports November Brought Semiconductor Sales back into 'Positive Territory'" http://www.edn.com/article/CA6713413.html?industryid=47037 With a positive attitude, the SIA (Semiconductor Industry Association) reported on November 2009 worldwide semiconductor sales this morning that showed growth on a month-over-month and year-over-year basis. =============================================================================== What is the statistical method for at-speed testing? ---------------------------------------------------- Jinjun Xiong (Ph.D.) Research Staff Member, IBM Thomas J. Watson Research Center [jinjun@us.ibm.com] Manufacturing testing becomes increasingly difficult in the nanometer manufacturing region because of the impacts of process variation on path delays. It has been frequently observed from manufacturing testing that different chips exhibit different speed limiting paths; and different set of paths may fail to meet the timing specification for different chips. Therefore, in order to maximize yield by shipping most chips to customers while limiting the percentage of bad chips shipped to customers (i.e., shipped-product quality level, or SPQL, which is based on the contract between the foundry and customers for guaranteed quality level), we want to leverage the statistical modeling capability of timing to select those "statistically critical" paths under different process conditions (e.g., metal 5 is thick and Leff is long, or metal 3 is thin and Leff is short) so that we can physically test all those paths in tester to see whether they in fact meet the timing specification. Because the path based delay testing is directly related to the chip performance specification, we need to test those paths at-speed, i.e., at or close to the rated functional clock frequency, for if those paths were not tested at-speed, the impact of those paths' performance variation would not be tested. The delay faults caused by process variation are static small delay defects that may happen at all locations of the chip simultaneously. Moreover, different from other types of delay faults, the process variation delay faults are correlated, i.e., the sizes of delay faults at different locations are correlated to each other. There are three types of mechanisms that cause this correlation. First is the global correlation, i.e., all chip process parameters are impacted by the same processing steps. For example, focus and dose of exposure during photo-lithography affect channel lengths of all transistors. Similarly chemical-mechanical polishing affects all wires on a particular metal layer simultaneously. Second is the within- die spatial correlation, i.e., devices or interconnect characteristics of the same region are likely to be similar than those that are far apart. Third is the structural correlation among paths, as different paths in a chip may share some common portion of the topology, be it devices or interconnects. Through recently developed block-based statistical static timing analysis techniques, all the above three types of correlation can be obtained for any two timing quantities when they are expressed in a parameterized form (be it linear, quadratic, or nonlinear) as functions of the underlying process parameters that are modeled as a random variables with certain distributions. Correlation among delay faults creates both difficulties and opportunities for delay testing. The difficulties lie in the fact that the number of combinations of different process parameters that can potentially cause some paths to fail timing is almost infinite, and trying to enumerate all those conditions is almost impossible. But the correlation among those faults also help to predict statistical characteristics of different delay variation scenarios. We can estimate the occurrence probability of any combination of process parameters, and by testing one path we can infer the likelihood of other paths being good or bad based on their correlation. Therefore, selecting paths that have the least correlation may not be a good strategy to detect this type of delay faults. To measure the quality of detecting delay faults caused by process variation, we need to define a test quality metric (TQM) for the set of paths selected for testing. Because the goal of testing is to screen out as many faulty chips as possible, we define the metric Q(Pi) as the probability that a tested chip has no timing violations conditional on test paths Pi passing at-speed testing. Mathematically, it can be written as (1) Q(Pi) = P(Chip is good | All test paths Pi passed testing). For the best testing quality, we would like to select a set of paths such that its TQM is maximized. Let S_C be the statistical chip slack. Now consider the subset of the chip that comprises the paths being tested during at-speed testing. Let S_Pi be the test slack of this subset of the chip Pi, i.e., the statistical minimum slack of all these test paths as S_Pi = min(S1,S2,...,Sn). Now we can express TQM in terms of chip slack S_C and test slack S_Pi as (2) Q(Pi) = P(S_C >= 0|S_Pi >= 0). By expanding (2) above, we obtain (3) Q(Pi) = P(S_C >= 0, S_Pi >=0 ) / P(S_Pi >=0). Because S_C represents all paths of the chip, it is always less than the slack of any set of paths Pi. Thus if chip slack S_C >= 0, it implies S_Pi >=0. So we can simplify the above equation (3) as (4) Q(Pi) = P(S_C >= 0) / P(S_Pi >=0). Since chip slack S_C is a characteristic of the whole chip and does not depend on the paths selected for testing, for the purpose of comparison, we can exclude the common numerator term depending on chip slack S_C, and thus use the denominator as a simpler surrogate TQM as (5) q(Pi) = P(S_Pi <= 0). It is clear that maximizing this surrogate TQM metric (5) is equivalent to maximizing the true TQM (2). For simplicity of presentation, we will also call this surrogate TQM as TQM. Next, we show that how the aforementioned TQM is related to the concept of process space coverage. In statistical timing, all timing quantities such as slack S are represented as functions of the underlying process parameters Xi (such as metal thickness or Leff). For the purpose of testing, we are only interested in those process conditions under which the manufactured chips have negative slack, or equivalently, fail to meet the timing. We formally define the mapping between a path slack Si to its process space coverage Wi as (6) Wi = {(X1,X2,...,Xn) | Si <= 0}, where (X1,X2,...,Xn) is a point in the n-dimensional process parameter space, or in other words, it represents a combination of different process parameter values. For a set of paths Pi, its corresponding process space coverage is the union of subspaces defined by each individual path, i.e., (7) W_Pi = W1 + ... + Wn , The entire process space of interests for testing is the subspace with negative chip slack S_C, which is denoted as (8) W = {(X1,X2,...,Xn) | S_C <= 0}. We can thus define a corresponding process space coverage metric for any set of paths Pi as (9) R(Pi) = || W_Pi || / || W || , where || . || is a Lebesgue measure (i.e., probability weighted area) of the process space. In terms of slack, we have (10) R(Pi) = P (S_Pi <= 0) / P (S_C <= 0). This gives a measure of the process space coverage for a set of paths. In other words, this set of paths defines (or covers) a subspace of the entire process space such that by testing this path set we would sort out all bad chips manufactured under those process conditions. Ideally, we would like to maximize this process space coverage metric by selecting a set of good paths for testing. In order to maximize the above process space coverage, we can similarly exclude the common denominator term depending on chip slack S_C that has nothing to do with the selection of path set Pi. And then use the numerator as another simpler surrogate metric for the process space coverage metric as (11) r(Pi) = P(S_Pi <= 0) In other words, maximizing process space coverage in (9) is equivalent to maximizing the surrogate coverage metric (11). Note that r(Pi) in (11) is exactly the same as the aforementioned surrogate TQM q(Pi) in (5). Therefore, maximizing TQM q(Pi) in (5) is equivalent to maximizing the process space coverage r(Pi) in (11). Since the computation of path slack S_Pi is based on results from SSTA, it is represented as a parameterized form. When the distribution is assumed to be Gaussian, we can easily compute the TQM through the error function. Once we have a well defined and easily computable metric for any given set of paths whose slacks are represented as a statistical parameterized form, all kinds of elegant path selection algorithms can be developed to solve this selecting "statistically critical" paths for at-speed testing. Suggested readings: [1] V. Iyengar et. al., Variation-Aware Performance Verification Using At-Speed Structural Test And Statistical Timing, ICCAD 2007. [2] V. Zolotov et. al., Statistical Path Selection for At-speed Testing, ICCAD 2008. (Best Paper Award Nomination) [3] J. Xiong et. al., At-Speed Testing in the Face of Process Variations, IEEE VLSI Test Symposium, May 2009. (Invited) [4] J. Xiong et. al., Statistical Multilayer Process Space Coverage for At-Speed Test, DAC 2009. (Best Paper Award Nomination) [5] J. Xiong et. al., Pre-ATPG Path Selection for Near Optimal Post-ATPG Process Space Coverage, ICCAD 2009. =============================================================================== Paper Submission Deadlines: ---------------------------- ISLPED'09 - International Symposium on Low-Power Electronics and Design Austin, TX Aug 18-20, 2010 Deadline: Mar 5, 2010 http://www.islped.org MEMOCODE'10 - International Conference on Formal Methods and Models for Codesign Grenoble, France Jul 26-28, 2010 Deadline: Mar 5, 2010 http://www-memocode2010.imag.fr BodyNets'10 - International Conference on Body Area Networks Corfu Island, Greece Sep 10-12, 2010 Deadline: Mar 22, 2010 (abstracts due Mar 10) http://www.bodynets.org PACT'10 - Int'l Conference on Parallel Architectures and Compilation Techniques Vienna, Austria Sep 11-15, 2010 Deadline: Mar 27, 2010 (abstracts due Mar 20) http://www.pactconf.org VLSI-SoC'10 - International Conference on Very Large Scale Integration and System on Chip Madrid, Spain Sep 27-29, 2010 Deadline: Mar 28, 2010 http://www.vlsi-soc.com ============================================================================== Upcoming Symposia, Conferences and Workshops: --------------------------------------------- HiPEAC'09 - Int'l Conference on High Performance Embedded Architectures & Compilers Pisa, Italy Jan 25-27, 2010 http://www.hipeac.net/conference ISSCC'10 - Int'l Solid-State Circuits Conference San Francisco, CA Feb 7-11, 2010 http://isscc.org/isscc/ DATE'10 - Design Automation and Test in Europe (sponsored by SIGDA) Dresden, Germany Mar 8-12, 2010 http://www.date-conference.com/ TAU'10 - International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (co-located with ISPD'10) San Fransisco, CA Mar 14-17, 2010 http://www.tauworkshop.com ISPD'10 - Int'l Symposium on Physical Design (sponsored by SIGDA) (co-located with TAU'10) San Francisco, CA Mar 14-17, 2010 http://www.sigda.org/ispd ISQED'10 - Int'l Symposium on Quality Electronic San Jose, CA Mar 22-24, 2010 http://www.isqed.org/ SPL'10 - Southern Conference on Programmable Logic Ipojuca, Brazil Mar 24-26, 2009 http://www.splconf.org/ ASYNC'10 - Int'l Symposium on Asynchronous Circuits and Systems Grenoble, France May 3-6, 2009 http://asyncsymposium.org ISCAS'10 - Int'l Symposium on Circuits and Systems Paris, France May 30 - June 2, 2010 http://iscas2010.org/ ============================================================================== Upcoming Funding Opportunities -------------------------------- IARPA Circuit Analysis Tools (CAT) Deadline: December 11, 2010 https://www.fbo.gov/index?s=opportunity&mode=form&id=48a747e2e1a32c522fba2d2d5aa39860&tab=core&_cview=0&cck=1&au=&ck= HHS Recovery Act - Beacon Community Cooperative Agreement Program Deadline: February 01, 2010 http://healthit.hhs.gov/portal/.../FOA_Beacon_Communities_120209.doc NIH Using Systems Science Methodologies to Protect and Improve Population Health (R21) Deadline: October 16, 2009 February 16, 2010 June 16, 2010 http://grants.nih.gov/grants/guide/pa-files/PAR-08-224.html Exploratory Collaborations With National Centers for Biomedical Computing (R21) Deadline: October 16, 2009 February 16, 2010 June 16, 2010 http://grants.nih.gov/grants/guide/pa-files/PAR-08-224.html DARPA NEOVISION2 Deadline: May 12, 2010 http://www.darpa.mil/dso/solicitations/baa09-58.htm DOE ASCR Research Computer Science Deadline: September 30, 2010 http://www.science.doe.gov/grants/FAPN09-01.html John von Neumann Postdoctoral Research Fellowship in Computational Science Deadline: December 04, 2010 http://www.cs.sandia.gov/VN_Web_Page/ Sabbaticals and Faculty Appointments Deadline: continuous http://www.nrel.gov/employment/sabbaticals.html DOD Young Investigator Program (YIP) - ONRBAA10-011 Deadline: January 29, 2010 http://www.onr.navy.mil/en/Contracts-Grants/Funding-Opportunities/Broad-Agency-Announcements.aspx NRC-NRL Cooperative Research Associateship Program Deadline: February 01, 2010 May 01, 2010 August 01, 2010 http://hroffice.nrl.navy.mil/jobs/postdoc.htm Microsystems Technology Office-Wide Broad Agency Announcement Deadline: February 17, 2010 https://www.fbo.gov/index?s=opportunity&mode=form&id=237f4e77cbc4152cbab89d024c3a0940&tab=core&_cview=0 Broadening Participation Research Initiation Grants in Engineering (BRIGE) - NSF 10-509 Deadline: February 25, 2010 http://www.nsf.gov/pubs/2010/nsf10509/nsf10509.htm Multidisciplinary University Research Initiative (MURI) - ONR BAA 10-002 Deadline: March 02, 2010 http://www.wpafb.af.mil/library/factsheets/factsheet.asp?id=9327 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.rdecom.army.mil/STTC/2006_N61339-05-R-0095__BAA_FY06_Amendment_0001.pdf Army Research Office (ARO) Broad Agency Announcement for Basic and Applied Scientific Research (W911NF-07-R-0003) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 ARL/ARO Core Broad Agency Announcement for Basic and Applied Scientific Research for Fiscal Years 2007 through 2011 (W911NF-07-R-0001) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 Advanced Scene Generation - BAA-RWK-08-0001 Deadline: Continuous https://www.fbo.gov/index?s=opportunity&mode=form&tab=core&id=d3dea412d6d7cb209cf35cfc8d4ef583&_cview=0 Multi-Agent Systems - BAA-RWK-08-0002 Deadline: Continuous https://www.fbo.gov/index?s=opportunity&mode=form&tab=core&id=20c833ef49fe6be1091a859879bc4edc&_cview=0 Systems and Software (AFOSR-BAA-2008-1) Deadline: Continuous http://www.wpafb.af.mil/shared/media/document/AFD-080212-048.pdf ERDC BAA - High Performance Computing (HPC) and Networking (ITL-3) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/BAA.pdf ERDC BAA - Computational Science and Engineering (ITL-1) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/BAA.pdf Artificial Intelligence Technologies (NRL-WIDE BAA-N00173-01) Deadline: Continuous http://heron.nrl.navy.mil/contracts/baa/index.htm Advanced Distributed Sensor Technologies Deadline: Continuous http://heron.nrl.navy.mil/contracts/baa/index.htm Information Management and Decision Architectures (NRL-WIDE BAA-N00173-01) Deadline: Continuous http://heron.nrl.navy.mil/contracts/baa/index.htm High Performance Computing on Massively Parallel Architectures (NRL-WIDE BAA-N00173-01) Deadline: Continuous http://heron.nrl.navy.mil/contracts/baa/index.htm NSF Cyber-Enabled Discovery and Innovation (CDI) - NSF 08-604 Deadline: February 04, 2010 http://www.nsf.gov/pubs/2010/nsf10506/nsf10506.htm?WT.mc_id=USNSF_25#budg_cst_shr_txt Power, Controls and Adaptive Networks (PCAN) Deadline: February 7, 2010 October 7, 2010 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13380 Sensors and Sensing Systems (SSS) Deadline: February 15, 2010 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13349 Fundamental Research Program for Industry/University Cooperative Research Centers (FRP) - NSF 10-507 Deadline: February 17, 2010 http://www.nsf.gov/pubs/2010/nsf10507/nsf10507.htm Cyber-Physical Systems (CPS) - NSF 08-611 Deadline: February 26, 2010 http://www.nsf.gov/pubs/2008/nsf08611/nsf08611.htm Software Development for Cyberinfrastructure (SDCI) - NSF 10-508 Deadline: February 26, 2010 http://www.nsf.gov/pubs/2010/nsf10508/nsf10508.htm Energy for Sustainability Deadline: March 03, 2010 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=501026&org=CBET Petascale Computing Resource Allocations (PRAC) - NSF 08-529 Deadline: March 17, 2010 http://www.nsf.gov/pubs/2008/nsf08529/nsf08529.htm Social-Computational Systems (SoCS) - NSF 09-559 Deadline: August 31, 2010 http://www.nsf.gov/pubs/2009/nsf09559/nsf09559.htm Engineering Design and Innovation (EDI) Deadline: January 15, 2010 - February 15, 2010 September 1, 2010 - October 1, 2010 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13340 Operations Research (OR) - PD 09-5514 Deadline: February 15, 2010 October 01, 2010 USDA Electronics/Computer Engineer - RA-08-065H (postdoctoral opportunity) Deadline: Continuous http://www.afm.ars.usda.gov/divisions/hrd/hrdhomepage/vacancy/08065.htm AFCEA AFCEA Ph.D. Fellowship Deadline: February 15, 2010 http://www.afcea.org/education/scholarships/graduate/grad3.asp Postdoctoral Fellowships JILA Postdoctoral Research Associates Deadline: Continuous http://jilawww.colorado.edu/employ/postdoc.html DOE: Richard P. Feynman (RPF) Postdoctoral Fellowship in Theory and Computing Deadline: Continuous http://www.lanl.gov/science/postdocs/appointments.shtml ORISE Research Participation Program for the U.S. Army Research Laboratory Deadline: Continuous http://www.orau.org/maryland/participants/arl_projects.htm Google Software Engineering Internship - Fall or Winter - North America Locations Deadline: Continuous http://www.google.com/support/jobs/bin/answer.py?answer=126265 Sun Microsystems Foundation, Inc. Academic Excellence Grant Program Deadline: Nov 30, 2009 Feb 26, 2010 May 31, 2010 http://www.sun.com/solutions/landing/industry/education/aeg.xml Sigma Delta Epsilon/Graduate Women in Science Eloise Gerry Fellowships Deadline: January 15, 2010 http://gwis.org/programs.html ============================================================================== Call for papers ACM TECS Special Issue on Embedded Systems for Real-time Multimedia (ESTIMedia 2009) -------------------------------- ACM Transactions on Embedded Computing Systems (TECS) Special Issue on Embedded Systems for Real-time Multimedia (ESTIMedia 2009) The Embedded Systems for Real-time Multimedia (ESTIMedia) provides an international workshop to promote research and exchange ideas about all areas related to applications of multimedia systems and in the evolution of system-on-chip design technology addressing the challenges (e.g., in terms of software, architectures, real-time systems, DSP, compilers, multimedia applications) that are faced during the design of hardware and software for multimedia embedded systems. To help promote the work presented at ESTIMedia 2009, ACM TECS is planning a special issue in 2010 on .the best of ESTIMedia 2009.. All authors who presented papers at ESTIMedia 2009 are invited to submit an extended version of their paper to ACM TECS for inclusion in this special issue. Besides submissions from ESTIMedia.09 any other high quality submissions that fits the topics of the special issues are welcome. Topics of interest include, but are not limited to: - Specification and modeling of multimedia systems - Multimedia systems design methodologies and case studies - Circuits and architectures for embedded multimedia architectures - Multimedia processors and reconfigurable architectures - Emerging trends (Systems-on-Chip, Networks-on-Chip, Game applications, etc.) - Validation and verification Software optimization and compiler techniques - Timing aspects of media streams Scheduling of media processing - Resource and QoS management methods - Temporal estimation and protection of media streams Real-time kernels, OS and middleware support Authors should submit their journal version at Manuscript Central adhering to the formatting instructions on the TECS Web page and indicate that you are submitting to the Special Issue on Embedded Systems for Real-time Multimedia. For additional questions please send an email to naehyuck@snu.ac.kr. Schedule: - Submission deadline: February 12, 2010 - Review results: June 30, 2010 - Final copy deadline: August, 2010 Guest Editors: - Naehyuck Chang, Seoul National University, Korea - Andy D. Pimentel, University of Amsterdam, Netherlands - Mladen Berekovic, TU Braunschweig, Germany ============================================================================== Call for papers ACM TODAES Special Section on Low Power Electronics and Design -------------------------------- ACM Transactions on Design Automation of Electronic Systems (TODAES) Special Section on Low Power Electronics and Design This special section focuses on recent advances in all aspects of low power electronics and design, ranging from process and circuit technologies, simulation and synthesis tools, to system level design and optimization. Authors who presented regular papers at ISLPED 2009 are specially invited to submit an extended version of their paper to ACM TODAES for inclusion in this special section. Besides submissions from ISLPED 2009 regular papers, any other high quality submissions that fits the topics of the special section are welcome. 1. Architecture, Circuits, and Technology 1.1. Technologies and Digital Circuits Emerging logic/memory technologies and applications; Low power device and interconnect design; Low power low leakage circuits; Memory circuits; Noise reduction; 3-D technologies; Cooling technologies; Battery technologies; Variation-tolerant design; Temperature-aware and reliable design 1.2. Logic and Microarchitecture Design Processor core design; Cache and register file design; Logic and RTL design; Arithmetic and signal processing circuits; Encryption technologies; Asynchronous design 1.3. Analog, MEMS, Mixed Signal and Imaging Electronics RF circuits; Wireless; MEMS circuits; AD/DA Converters; I/O circuits; Mixed signal circuits; Imaging circuits; Analog noise; Circuits to support emerging technologies; DC-DC converters 2. Design Tools, System and Software Design 2.1. Design Tools Energy simulation and estimation tools that operate at the circuit/gate level, RT level, behavioral level, and algorithmic level; Variation-aware design; Physical design and interconnects 2.2. System Design and Methodologies Microprocessor, DSP and embedded systems design; FPGA and ASIC designs; System-level power- and thermal-aware design; System-level reliability- and variability-aware design 2.3. Software Design and Optimization Power- and thermal-aware software design, scheduling, and management; Application- level optimizations; Wireless and sensor networks; Emerging applications The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25. For additional questions please send an email to naehyuck@snu.ac.kr. Schedule: Paper submission deadline: February 22, 2010 Editorial decisions: June 7, 2010 Camera-ready manuscripts due date: July 1, 2010 Target Issue: October, 2010 Guest Editors: Naehyuck Chang, Seoul National University, Korea JöHenkel, Karlsruhe Institute of Technology (KIT), Germany =============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. 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