=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membership. Circulation: 2,700 =============================================================================== 1 February 2009 ACM/SIGDA E-NEWSLETTER Vol. 39, No. 2 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Soheil Ghiasi Contributing author: Matthew Guthaus Contributing author: Umit Y Ogras Contributing author: Marc Riedel Contributing author: Lin Yuan (2) What Are the Challenges and Solutions for Parallel Processing in EDA Applications? Contributing author: Tom Spyrou, Cadence Design Systems From: Deming Chen (3) Paper Submission Deadlines From: Debjit Sinha (4) Upcoming Conferences and Symposia From: Debjit Sinha (5) Upcoming Funding Opportunities From: Qinru Qiu (6) Call for Papers: ISLPED 2009 From: Naehyuck Chang (7) Call for Participation: ISPD 2009 Clock Tree Synthesis Contest From: Matthew R. Guthaus =============================================================================== Dear ACM/SIGDA members, In this issue, we have included the new "What Are the Challenges and Solutions for Parallel Processing in EDA Applications?" from Tom Spyrou (Cadence Design Systems). We welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Qing Wu, E-Newsletter Editor; Matthew Guthaus, E-Newsletter Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Debjit Sinha, E-Newsletter Associate Editor; Lin Yuan, E-Newsletter Associate Editor; Soheil Ghiasi, E-Newsletter Associate Editor; Deming Chen, E-Newsletter Associate Editor; Umit Y Ogras, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "ACM Names 44 Fellows for Contributions to Computing and Information Technology" http://newswire.ascribe.org/cgi-bin/behold.pl?ascribeid=20090115.074243 ACM has recognized 44 of its members for their contributions to computing technology that have generated a broad range of innovations to industry, commerce, entertainment, and education. The 2008 ACM Fellows, from the world's leading universities, industries, and research labs, created advances in computer theory as well as practice. These technology developments have consistently demonstrated their crucial role in forming the foundation for sustained economic growth in an information-based society. Out of this year's 44 newly minted ACM Fellows, three are from the CAD community: Jason Cong, Jonathan Rose, and Rob Rutenbar. "Rhines Challenges Pessimistic Prognosis for EDA" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=213001104 Walden Rhines, chairman and CEO of Mentor Graphics Corp., stuck a positive note during a keynote address at the DesignCon program here Tuesday (Feb. 3), presenting data that he said debunked many commonly held pessimisms about EDA and the broader semiconductor industry. Contrary to popular belief, the number of EDA vendors is not shrinking due to consolidation, migration to new technology nodes is not slowing, EDA tools are not becoming too expensive and chip vendors are not rushing to single-vendor tool flows, Rhines said. "Comment: EDA Bashing" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=213000376 It seems that lately if you want to be considered an authority on the EDA industry you must be negative about it, in fact you must say the most pessimistic thing you can muster about its technology, its finances, and its prospects. I agree that there is plenty of reasons to be depressed, yet no one ever constructed a recovery on negativism. Are we doing the best we can? Of course not, otherwise all would have been accomplished and we should go find something else to do. Are there future opportunities? of course there are. I will give you one hint: redefine "system level". "Standardize What?" http://www.the-scientist.com/article/display/55381/ The original assembly standard developed by MIT researcher Tom Knight laid the groundwork for the notion of mix-and-match biological parts. But technical protocols for assembling DNA are far from the only element of synthetic biology that needs to be standardized for the idea of parts sharing to take off. Once you make a part, you need to specify its characteristics . how strongly it expresses a particular gene, for example - for others to use it. "Japan's Electronics Industry Shocked By $22 Billion in Losses" http://www.eetimes.com/news/latest/showArticle.jhtml Japan's electronics industry, a key driver for the nation's economy and home to Hitachi, Panasonic and Sony, is facing the biggest crisis since 2002 - and possibly its biggest shock ever. "U.S. Taps IBM For 20 Petaflops Computer" http://www.eetimes.com/news/latest/showArticle.jhtml The U.S. government has agreed to buy two supercomputers from IBM Corp., including one to be in use in 2012 that will ultimately scale to 20 petaflops, an estimated ten times the performance of today's most powerful system. Terms of the deal were not immediately released. "Researchers Advance Quantum-Memory-Retention Time" http://www.edn.com/article/CA6632385.html?industryid=47037 Researchers at the Georgia Institute of Technology have announced a significant advance in the retention time of multiatom quantum-memory devices-from a previous maximum of 32 usec to 7 msec. "Xilinx FPGA Introductions Hint at New Realities" http://www.edn.com/article/CA6633947.html?industryid=47037 Xilinx announced its 40-/45-nm generation of FPGAs with the usual accoutrements of a major product launch, but also with several major departures from the Moore's-Law driven traditions of the FPGA industry. The company announced two new families, the Virtex-6 family based on UMC's 40-nm gp process, and the Spartan-6 family built on Samsung's half-node-earlier 45-nm process. "Video: Xilinx CEO Sees 'Programmable Imperative'" http://www.eetimes.com/news/latest/showArticle.jhtml Moshe Gavrielov, president and CEO of programmable logic supplier Xilinx Inc., kicked off a recent press briefing here by making the case that market and technology forces have finally aligned to create a tipping point whereby field programmable gate arrays (FPGAs) are displacing traditional application specific integrated circuits (ASICs) for many applications. "ARM Raises Revenue, Profit in Q4, Sees Growth in 2009" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=213000664 Processor technology licensor ARM Holdings plc (Cambridge, England) was able to benefit from a one-quarter delay inherent in its way of recognizing IP revenue and turn in positive Q4 and full financial results. While acknowledging the Q4 downturn seen elsewhere ARM was positive about its own prospects in 2009. "EE Times Updates List of Emerging Startups to Version 8.0" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=213000246 The list of EE Times 60 Emerging Startups, first published in April 2004, has been updated to version 8.0, reflecting the latest corporate, commercial, technology and market conditions. Twenty-three companies have been brought onto the Silicon 60. "First 2 TB Hard Drives From WD" http://www.eeproductcenter.com/memory/brief/showArticle.jhtml?articleID=213000276 WD announced the first 2 terabyte (TB) hard drive - the world's highest capacity drive and the latest addition to WD's popular, environmentally friendly, cool and quiet, WD Caviar Green hard drive family. This new 3.5-inch platform is based on WD's 500 GB/platter technology (with 400 Gb/in2 areal density) with 32 MB cache, producing drives with capacities of up to 2 TB. "ST, Ericsson Move Ahead on Wireless Joint Venture" http://www.edn.com/article/CA6634281.html?industryid=47037 Ericsson Mobile Platforms merges into ST-NXP Wireless as TI and Freescale continue to make changes to their wireless businesses. Change continues to come to the mobile world, as STMicroelectronics and Ericsson today announced the closing of their agreement merging EMP (Ericsson Mobile Platforms) and ST-NXP Wireless into a 50/50 joint venture. "A Robomedic for the Battlefield" http://www.technologyreview.com/biomedicine/22045/ A snakelike robotic arm may one day medically attend to soldiers as they are carried off the battlefield. "Wireless Detectors for Dementia" http://www.technologyreview.com/computing/22043/?a=f Researchers hope that radio transmitters can warn of cognitive decline earlier. Researchers at the University of South Florida (USF) have developed a wireless network that evaluates walking patterns in an attempt to detect early signs of dementia. =============================================================================== What Are the Challenges and Solutions for Parallel Processing in EDA Applications? ----------------- Tom Spyrou, Distinguished Engineer Cadence Design Systems EDA applications, some of the most complex and compute intensive software applications ever written, need to aggressively pursue parallel processing in order to continue to improve performance and allow the design and verification of the coming generations of complex integrated circuits. In the past, the frequency scaling of general purpose microprocessors allowed EDA applications to get the performance improvements they needed essentially for free. However, in 2004, with the cancellation of some high profile microprocessor projects, frequency scaling was brought to a virtual halt. The power consumption of the frequency scaled designs was too great. P = C ×(V^2) ×F. Voltage could not be scaled down enough to offset the power needed to increase frequency any further. Going forward we will not see any major increase in the frequency of general purpose microprocessors. Instead we are seeing the vast real estate on smaller geometry chips being used to place multiple processors on a single chip. Traditionally, most computer software and most EDA applications and algorithms have been written for serial computation. Except in the cases where the compute time was extremely long, or in cases where doing the computation in parallel was trivial to implement, EDA applications have been single threaded. For example, Library Characterization, and RTL Synthesis have utilized parallel processing for years. Cells and modules can be run in parallel using a simple Makefile and the results are easily integrated. Design Rule Checking and Optical Proximity Correction have also been run in parallel since they can make use of simple spacial partitioning to divide the work. EDA applications and the EDA work flow as a whole will not achieve the scaling that is needed by only focusing on the easy to parallelize problems. For a significant speedup in a work flow to be achieved nearly every step of that work flow needs to be run in parallel. Amdahl.s law is used to predict the maximum expected improvement to an overall system when only part of the system is improved. It is often used in parallel computing to predict the theoretical maximum speedup using multiple processors. The speedup of a program in parallel computing is limited by the time needed for the sequential fraction of the program. For example, if a program needs 50 hours using a single processor core, and a particular portion of 5 hours (10%) can not be parallelized, while the remaining promising portion of 45 hours (90%) can be parallelized, then regardless of how many processors we devote to a parallelized execution of this program, the minimum execution time can not be less than that critical 5 hours, which is a 10X speedup. Amdahl.s law shows us that if we only recode 50% or less of our tool flow to be parallel, then we will not be able to make optimal use of today.s existing multi-core machines which have 8 or 16 cpus in a box, much less be able to scale to the coming generation of machines where 32, 64 and 128 processors will exist in a box. In the Digital IC implementation area of EDA software, there are many steps in the design flow from netlist to tape-out. There is timing analysis, placement, clock distribution synthesis, physical optimization, routing, noise analysis and various chip finishing steps. In order for the users of EDA tools and specifically Digital IC implementation tools to gain the benefit of multi-core chips and multi-processor machines, every step in the flow will need to be recoded to support parallel computing. There will need to be end to end parallel processing. This need for end to end parallel processing also extends to each of the major parts of the EDA industry. Digital IC implementation software is a good representative example. A coarse grained partitioning of the problem will not suffice in this example. Coarse grained approaches need to have a serial step where the work is partitioned and another where it is re-assembled. This partitioning in Digital design applications on large designs can take significant time and will often be the bottleneck. A fine grained division of work in the core algorithms will be necessary to achieve good scalability. Each of the algorithms will need to be parallelized in their respective cores. In EDA tool flows there has been, for some time, a goal to allow users to operate in a single consolidated environment. This has been for ease of use and also to avoid the runtime associated with translating data from one system to another. EDA users have been reluctant to use a single vendor flow and often purchase and use tools from various vendors to achieve best in class point tool usage. The need for every step to be parallelized will be another driver to a consolidated system since data translation between systems is generally a painfully slow serial step. It would not make sense to optimize for a point tool at the expense of reducing the total system throughput to the degree which would happen in a highly parallel environment just because of a painfully slow serial translation step. Distributed processing utilizes a network of machines. A supervisor process invokes several worker processes and sends them messages with work to do. The workers usually can see the file system of the supervisor and can load the same data or subset of data as the supervisor. The workers complete their tasks and return results in messages to the supervisor. Messages are generally sent with TCP/IP sockets. Machines are managed by a resource management system like LSF or Sun Grid. On the other hand, multi-threaded programming involves utilizing multiple cpu.s on the same machine. Each cpu has a thread of control which shares memory with the supervisor and other worker threads. Since all workers can share the same data it needs to be synchronized in a manner which ensures that two workers don.t write at the same time and which ensures race conditions between one thread reading and another writing do not happen. Distributed applications can scale to as many computers as exist in the cloud or farm and which have reasonable connectivity for the data transfer requirements of the process at hand. Data is not shared and there is significant overhead for passing the data around. There also may be the need to duplicate data on all machines for some applications. Multi-threaded programming can only scale to the number of cpus in one box. All of the data structures are shared so there is no overhead to copy or duplicate data. However, the code has to be .thread safe., meaning that is guaranteed that it will not have race conditions as described above. EDA applications which require any significant data synchronization will prefer the multi-threaded model. The amount of data used in EDA applications can be on the order of 100Gigabytes or even much more in some applications. Duplicating this volume of data or a fraction of it will be too expensive in terms of transfer time and total RAM cost across the supervisor and worker machines when compared to benefits of sharing the data among local processors. For many legacy applications paralellizing more than 95% of the total runtime will be difficult. This means that the theoretical maximum speedup from Amdahl's law is 20X and that most applications will not scale cost effectively much beyond 16 cpus which are already available in one box. With future multi-core computers the cloud of computers will be encased in a single box. We should therefore see a trend toward less distributed and more multi-threaded computing in EDA applications. Scaling beyond 16 cpus will require a significantly new way of software engineering of these problems which focuses on elimination or minimization of serial steps. The change from single threaded frequency scaling to multi-core scaling through parallel processing has significant implications on EDA Software and algorithms. Many legacy applications will be retrofitted and many more will have to be re-written. The entire work flow of the user will need to be made parallel, or the scalability of the work flow will be severely limited by Amdahl's law. Creating a design flow with this type of end to end multi-processing will be one of the largest changes ever in EDA software engineering. The core algorithms in many cases may remain the same, but the construction of the applications in which they run will be affected dramatically. If done well, EDA users will benefit from the inexpensive parallel computing now possible with multi-core chips and will see runtime improvements much more dramatic than frequency scaling has ever given. References: http://en.wikipedia.org/wiki/Amdahl's_law http://en.wikipedia.org/wiki/Cloud_computing http://en.wikipedia.org/wiki/Multithreading_(computer_hardware) ============================================================================== Paper Submission Deadlines: ---------------------------- ISLPED'09 - International Symposium on Low-Power Electronics and Design San Francisco, California Aug 19 - 21, 2009 Deadline: Mar 2, 2009 http://www.islped.org MEMOCODE'09 - International Conference on Formal Methods and Models for Codesign Cambridge, MA Jul 13-15, 2009 Deadline: Mar 6, 2009 http://csg.csail.mit.edu/Memocode2009/ SBCCI'09 - Symposium on Integrated Circuits and Systems Design Chip on the Dunes Natal, Brazil Aug 31 - Sep 3, 2009 Deadline: Mar 24, 2009 http://www.sbc.org.br/sbcci VLSI-SoC'09 - International Conference on Very Large Scale Integration Florianopolis, Brazil Oct 12-14, 2009 Deadline: Mar 28, 2009 http://www.inf.ufrgs.br/vlsisoc Edutech'09 Florianopolis, Brazil Oct 15-16, 2009 Deadline: Apr 30, 2009 http://www.inf.ufrgs.br/edutech ============================================================================== Upcoming Symposia, Conferences and Workshops: --------------------------------------------- ISSCC'09 - Int'l Solid-State Circuits Conference San Francisco, CA Feb 8-12, 2009 http://isscc.org/isscc/ TAU'09 - International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems Austin, TX Feb 23-24, 2009 http://www.tauworkshop.com ISQED'09 - Int'l Symposium on Quality Electronic San Jose, CA Mar 16-18, 2008 http://www.isqed.org/ ISPD'09 - Int'l Symposium on Physical Design (sponsored by SIGDA) San Diego, CA Mar 29 - Apr 1, 2009 http://www.ispd.cc/ SPL'09 - Southern Conference on Programmable Logic São Carlos, Brazil Apr 1-3, 2009 http://www.splconf.org/ FMGALS'09 - 4th International Workshop on Formal Methods for Globally Asynchronous and Locally Synchronous Designs Nice, France Apr 24, 2009 http://memocode.irisa.fr/FMGALS09 ISCAS'09 - Int'l Symposium on Circuits and Systems Taipei, Taiwan May 24-27, 2009 http://iscas2009.org/ ============================================================================== Upcoming Funding Opportunities -------------------------------- DARPA Strategic Technologies (BAA 08-10) Deadline: February, 2009 http://www.darpa.mil/sto/solicitations/BAA08-10/index.html DOD Modeling and Simulation for Information Systems Research Deadline: FY 10 should be submitted by June 1, 2009 http://fedbizopps.cos.com/cgi-bin/getRec?id=20061030a9 Test and Evaluation Deadline: July 2009 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Cognition and Neuroergonomics Collaborative Technology Alliance (CTA) - W911NF-08-R-0014 Deadline: July 01, 2009 http://fedbizopps.cos.com/cgi-bin/getRec?id=20080811a12 Cognitive Neuroscience (CNS) or Other Emerging or Leap-Ahead Technologies That Offer to Dramatically Advance Submarine Sonar or Other Advanced Underwater Systems Deadline: July 2009 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Information Warfare: Offensive and Defensive Counterinformation - BAA-06-12-IFKA Deadline: Continuous until December 2009 https://www.fbo.gov/index?s=opportunity&mode=form&id=5a4214baae590a1808f3077a0e7b9244&tab=core&_cview=1 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.rdecom.army.mil/STTC/2006_N61339-05-R-0095__BAA_FY06_Amendment_0001.pdf Army Research Office (ARO) Broad Agency Announcement for Basic and Applied Scientific Research (W911NF-07-R-0003) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 ARL/ARO Core Broad Agency Announcement for Basic and Applied Scientific Research for Fiscal Years 2007 through 2011 (W911NF-07-R-0001) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 Systems and Software (AFOSR-BAA-2008-1) Deadline: Continuous http://www.wpafb.af.mil/shared/media/document/AFD-080212-048.pdf NSF Expeditions in Computing Deadline: (Full Proposal Deadline) February 10, 2009, and February 10, annually thereafter (Preliminary Proposal) September 10, 2009, and September 10, annually thereafter http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=503169&org=CISE&from=home Strategic Technologies for Cyberinfrastructure (STCI) Deadline: February 12, 2009 August 13, 2009 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500066 Operations Research (OR) Deadline: February 15, 2009 October 01, 2009 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13341 Engineering Design and Innovation (EDI) Deadline: February 15, 2009 October 01, 2009 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13340 Cyber-Physical Systems (CPS) Deadline: February 27, 2009 http://www.nsf.gov/pubs/2008/nsf08611/nsf08611.htm Energy for Sustainability Deadline: March 02, 2009 September 15, 2009 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=501026&org=CBET Foundations of Data and Visual Analytics (FODAVA) Deadline: April 2, 2009 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=501081&org=CISE&from=home CISE Cross-Cutting Programs: FY 2009 and FY 2010 - NSF 08-578 Deadline: (Medium Projects) August 1 to 30, 2009, and August 1 to 30, annually thereafter (Large Projects) November 1 to 28, 2009, and November 1 to 28, annually thereafter (Small Projects) December 1 to 17, 2009, and December 1 to 17, annually thereafter http://www.nsf.gov/pubs/2008/nsf08578/nsf08578.txt USDA Electronics/Computer Engineer - RA-08-065H (postdoctoral opportunity) Deadline: Continuous http://www.afm.ars.usda.gov/divisions/hrd/hrdhomepage/vacancy/08065.htm =============================================================================== Call for Papers ----------------------- ISLPED 2009 - CALL FOR PAPERS International Symposium on Low-Power Electronics and Design San Francisco, California August 19 - 21, 2009 http://www.islped.org The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of recent advances in all aspects of low power design and technologies, ranging from process and circuit technologies, simulation and synthesis tools, to system level design and optimization. Specific topics include, but are not limited to, the following two main areas, each with three sub-areas: PROGRAM TRACKS: 1. Architecture, Circuits, and Technology 1.1. Technologies and Digital Circuits Emerging logic/memory technologies and applications; Low power device and interconnect design; Low power low leakage circuits; Memory circuits; Noise reduction; 3-D technologies; Cooling technologies; Battery technologies; Variation-tolerant design; Temperature-aware and reliable design 1.2. Logic and Microarchitecture Design Processor core design; Cache and register file design; Logic and RTL design; Arithmetic and signal processing circuits; Encryption technologies; Asynchronous design 1.3. Analog, MEMS, Mixed Signal and Imaging Electronics RF circuits; Wireless; MEMS circuits; AD/DA Converters; I/O circuits; Mixed signal circuits; Imaging circuits; Analog noise; Circuits to support emerging technologies; DC-DC converters 2. Design Tools, System and Software Design 2.1. Design Tools Energy simulation and estimation tools that operate at the circuit/gate level, RT level, behavioral level, and algorithmic level; Variation-aware design; Physical design and interconnects 2.2. System Design and Methodologies Microprocessor, DSP and embedded systems design; FPGA and ASIC designs; System-level power- and thermal-aware design; System-level reliability- and variability-aware design; Power- and thermal-aware multi- and many-core SoC design 2.3. Software Design and Optimization Power- and thermal-aware software design, scheduling, and management; Application-level optimizations; Wireless and sensor networks, and NoC; Emerging applications; Green computing IMPORTANT DATES: * Technical paper submission deadline: March 2, 2009 * Invited talks, panels and tutorial proposals deadline: April 6, 2009 * Notification of paper acceptance: May 9, 2009 * Camera-ready version due: May 25, 2009 * Exhibition proposal deadline: May 29, 2009 * Low-power design contest submission deadline: June 5, 2009 TECHNICAL PAPER SUBMISSIONS: Submissions should be full-length papers of up to 6 pages (double-column format, font size 9pt to 10pt), including all illustrations, tables, references and an abstract of no more than 100 words. Electronic submission in pdf format only via the web (http://www.islped.org) is required. Papers exceeding the six-page limit and/or identifying the authors will be automatically rejected. Submitted papers must describe original work that will not be announced or published prior to the Symposium and that is not being considered or under review by another conference at the same time. Accepted papers will be published in the Symposium Proceedings and included in the ACM Digital Library. Authors of a few selected papers from the Symposium will also be given an opportunity to submit enhanced versions of their papers for publication in a special issue of a reputed journal. INVITED TALKS, EMBEDDED TUTORIALS AND PANELS: Proposals for invited talks, embedded tutorials, and the panel should be sent to TPC Co-Cahirs: Naehyuck Chang, Seoul National University, naehycuk@snu.ac.kr, Tahir Ghani, Intel, tahir.ghani@intel.com. EXHIBITIONS: Companies interested in exhibiting at the Symposium should contact the Exhibits Chairs by May 29, 2009. DESIGN CONTEST: Low Power Design Contest to provide a forum for universities and research organizations to showcase original power-aware designs and to highlight the innovations and design choices targeted at low power. The goal is to encourage and highlight design-oriented approaches to power reduction. Entries should be submitted electronically in PDF format only to the Design Contest Co-Chairs: Kevin (Yu) Cao, Arizona State University, Yu.Cao@asu.edu and Chirs Kim, University of Minnesota, chriskim@umn.edu. Entries identifying the authors will be automatically rejected. SPONSORS: ACM SIGDA and IEEE Circuits and Systems Society with technical support from the IEEE Solid-State Circuits Society and the IEEE Electron Devices Society. =============================================================================== Call for Participation ----------------------- ACM International Symposium on Physical Design 2009 http://www.ispd.cc/ Clock Tree Synthesis Contest Call for Participation We gladly announce the first clock tree synthesis contest! During the past four years, ISPD has been hosting placement and global routing contests with interesting industrial benchmarks. In ISPD 2009, we continue this great tradition and host new clock tree synthesis contest. Clock tree synthesis is one of the most fundamental CAD problems. Yet, with ever increasing demands of high performance in today's VLSI chips, we cannot overemphasize the importance of clock tree synthesis. In a typical industrial physical design flow, a separate dedicated clock tree synthesis process is applied to build high performance minimum skew clock tree. And we think this problem well deserves as a new contest topic. You are invited to participate! The next ISPD is being held March 29-April 1, 2009 in San Diego, California. The clock tree synthesis contest will be held again just prior to the symposium. To participate, the contestant must register by January 15, 2009. Registering will allow you to receive a few sample benchmarks and relevant scripts that you can test your tools. After all, the contest chair (Dr. Cliff Sze) will run the tools from all teams on his platforms. Therefore, each contestant must submit a final clock tree synthesis executable by March 1, 2009. The quality of clock tree solution will be measured by the maximum skew of any arbitrary pair of sinks with a given slew constraint. In other words, all sinks have to meet a given slew constraint and the clock tree solution with the lowest skew value wins the contest. No CPU time or clock latency or power consumption will be considered this time for simplicity. A clock tree solution must be obstacleaware, which means there will be blockages in the area and your clock tree cannot have buffers on top of these blockages. Clock wires, however, can go over the blockages. This is because normally there exist dedicated metal layers for global clock distribution. For skew measurement, we encourage you to use hspice simulation tool that should be available in public domain. (At each institution, you should be able to find hspice simulation tool for your VLSICAD courses. If you cannot find the tool, let us know.) Similar to previous contests, through out the event, a new set of industrial clock tree benchmarks will be released to further accelerate developments in this area. The details of the sizes of the contest designs will be posted to ISPD website later. In general, the input and output formats should be similar to global routing contest formats. Please make note of the following * Cliff Sze from IBM Research will be chairing the contest. Any question about the contest should be directed to csze@us.ibm.com, with subject "ISPD2009-CTS". * All contest-related materials will be updated at http://www.ispd.cc/contests * To enter the contest, you must register by January 15, 2009 by sending an email to the contest chair. Include the name of the tool, the names of the developers, the affiliation and one page description of your algorithm. * On November 16, 2008, we will post a few sample benchmarks, the exact format of inputoutput files, bufferwire library and their parasitic models for hspice simulation. Also, a script to translate your global routing output file into simulation input file will be provided. * By February 1, 2009, each team must submit an executable and a script to test running it on our platforms. This is very important to make sure that our simulation results match yours. * By March 1, 2009, a contest executable and a script must be submitted to the contest chair. * Results of the contest will be announced during ISPD 2009. ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ============================================================================== This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To unsubscribe, send an email to listserv@listserv.acm.org with "signoff sigada-announce" (no quotes) in the body of the message. Please make sure to send your request from the same email as the one by which you are subscribed to the list. ==============================================================================