=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membership. Circulation: 2,700 =============================================================================== 15 October 2008 ACM/SIGDA E-NEWSLETTER Vol. 38, No. 20 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Soheil Ghiasi Contributing author: Matthew Guthaus Contributing author: Umit Y Ogras Contributing author: Marc Riedel Contributing author: Lin Yuan (2) What is Wireless Health? Contributing author: Majid Sarrafzadeh, UCLA From: Deming Chen (3) Paper Submission Deadlines From: Debjit Sinha (4) Upcoming Conferences and Symposia From: Debjit Sinha (5) Call for Papers: IEEE Design and Test Special Issue on 3D IC Design and Test of Computers From: Deming Chen (6) Call for Papers: 2009 International Symposium On Networks-On-Chip From: Davide Bertozzi (7) Call for Papers: TAU 2009 From: Peng Li (8) Call for Papers: DATE 2009 Friday Workshop on 3D Integration From: Geert Van der Plas (9) Upcoming Funding Opportunities From: Qinru Qiu =============================================================================== =============================================================================== Dear ACM/SIGDA members, In this issue, we have a new "What is Wireless Health?" column from Prof. Majid Sarrafzadeh of UCLA. Our target is to publish a new and original "What Is ..." column every month. We welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Qing Wu, E-Newsletter Editor; Matthew Guthaus, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Debjit Sinha, E-Newsletter Associate Editor; Lin Yuan, E-Newsletter Associate Editor; Soheil Ghiasi, E-Newsletter Associate Editor; Deming Chen, E-Newsletter Associate Editor; Umit Ogras, E-Newsletter Associate Editor; ============================================================================== SIGDA News ----------------------- "Cadence CTO Blasts Critics" http://www.eetimes.com/news/latest/showArticle.jhtml Responding to harsh criticism touched off by the departure of senior executives, the chief technology officer of Cadence Design Systems Inc. dismissed calls to spin off parts of the EDA company. "Philips Shows Magic Wands and Electric Dresses" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=211201025 Research tour reveals open model for projects like 3DTV. A magic wand, an electric dress, an intelligent building and a high definition stereo 3-D TV. These are just four of the concepts driving work at the sprawling headquarters campus of Philips Research here. "AMD Q3 Financials Improve, But Losses Still A Concern" http://www.edn.com/article/CA6606328.html Looking to Q4 and noting the macroeconomic environment, CEO Dirk Meyer said he does not expect the quarter to have its usual strength, but "it does not seem like a disaster." Although financials are improving at Advanced Micro Devices Inc and the MPU maker's GPU revenue increased by 55% in the September quarter, analysts are still concerned on the company's continuing losses. "NTT DoCoMo, Renesas, Fujitsu, Sharp Develop HSUPA Mobile Phone Platform" http://www.edn.com/article/CA6605931.html The announcement is further evidence of mobile industry partnering trends that include both chipmakers and handset makers. "Start-Up Claims Commercial Application of Silicon Ink" http://www.edn.com/article/CA6605989.html The announcement signals one of the first commercial application of silicon ink, a highly anticipated market opportunity that could see high-speed presses print millions of throwaway electronic components at a fraction of the cost of silicon-based circuitry. "Mobility Boosts Intel Q3, Wall Street Sighs With Relief" http://www.edn.com/article/CA6605604.html?industryid=47037 CEO Paul Otellini says the "Atom family is off to a very good start" as Intel's mobility group chips in more than 45% of the MPU leader's total $10.2 billion Q3 revenue. Although Intel has reduced its capital forecast for the year, the company cautions that it is not reducing ramp rate on 45 nm and is not pushing out 32-nm work. "Readers' Choice: Most-Clicked-On Electronic News Today Q3 Content" http://www.edn.com/article/CA6605741.html?industryid=47037 With Q3 2008 now comfortably behind us and the earnings reports pouring in, Electronic News Today presents its 20 most-clicked-on articles and blogs from the September quarter. Engineering employment, Apple, and solar projects are among the topics that got readers attention in Q3. Read on for a list of EDN's daily newsletter's top Readers' Choice content. "Replacing Hard-Disk Drives With Solid State: A Challenging But Opportune Prospect For Vendors" http://www.edn.com/article/CA6604442.html?industryid=47037 Falling NAND prices and improved controllers could make SSDs a viable option in mainstream computers. But the storage still faces obstacles to rapid adoption, including lack of interface designs robust enough to handle and prioritize data processing in PCs, as well as a crowded vendor market. "Samsung Enters US Notebook, Netbook Market" http://www.edn.com/article/CA6605188.html?industryid=47037 As PC sales in the United States continue to defy economic trends, Samsung comes to the market with five notebooks and one netbook that it believes will allow it access to the business and consumer segments. "IBM Extends China Research" http://www.edn.com/article/CA6605336.html?industryid=47037 Noting the "pool of science and engineering talent" in the region, IBM opens its first new research facility in 10 years in Shanghai as an extension of the existing IBM China Research Laboratory. IBM Corp today announced the opening of a Shanghai R&D facility, its first new research facility in almost 10 years. "Renesas, Panasonic to Develop 32-nm SoCs" http://www.edn.com/article/CA6603730.html?industryid=47037 The companies are jointly developing transistor and LSI interconnect technology in an effort to realize low power consumption and high-speed signal processing capabilities. Continuing their joint process technology development that has been happening since 1998, Tokyo-based electronics giant Panasonic Corp and semiconductor company Renesas Technology Corp reported today that they are collaborating to develop the elemental process technologies for 32-nm SoCs and are confident that this technology can be applied to products that are currently in mass production. =============================================================================== What is Wireless Health? ---------------------------- Majid Sarrafzadeh, Computer Science Department University of California at Los Angeles Recent advances in the electronics industry and wireless communication have enabled innovative domains of applications to evolve. Embedded processors and systems have become widely used in people's everyday life in various applications ranging from mobile communication to automotive industries to medical applications. The groundswell of wellness healthcare programs and patient management emphasize more involvement by patients themselves. This paradigm largely requires that patient information be readily available at the point of care, regardless of which physician the patient sees. The current proliferation of broadband wireless services, along with more powerful and convenient handheld devices, is helping introduce real-time monitoring and guidance for a wide array of patients. Low-cost sensors and wireless systems can now create a constantly vigilant and pervasive monitoring capability at home, at work, and in conventional point-of-care environments [4][5] (e.g., primary care physician offices, outpatient clinics, rehabilitation centers). Indeed, a large research community and a nascent industry is beginning to connect medical care with technology developers, vendors of wireless and sensing hardware systems [1], network service providers, and enterprise data management communities. Wearable devices focusing on personal health, rehabilitation, and early disease detection are now being prototyped. All these have led us to the new notion of "Wireless Health" A variety of applications lie within the Wireless Health category. Initially, wireless health (which few years ago was known as Telehealth) mainly referred to a remote consultation of physicians located in different geographical locations for diagnosis and treatment advices. Later on, with advances made in robotics and high-speed communication, telesurgery applications emerged where a surgeon performs surgery on a patient when he/she is not physically in the same location. Nowadays, all aspects of heath care ranging from physiological signal monitoring [2], diagnosis, rehabilitation [3], and treatment to surgical procedures utilize advance technologies and are generally refereed to as wireless health. Telehealth systems are not only used to make health care applications available in remote areas, such as homes, schools, nursing homes, and military camps but also in ubiquitous infrastructures that can improve the quality of overall health care. You can find many interesting research challenges and projects along with further information on the subject at the following location: http://www.wirelesshealth.ucla.edu/ http://er.cs.ucla.edu/ http://www.ascent.ucla.edu/ References: [1] Foad Dabiri, Tammara Massey, Hyduke Noshadi, Hagop Hagopian, and Majid Sarrafzadeh, "Lightweight Medical Bodynets," In Proceedings of the Second International Conference on Body Area Networks, Florence, Italy, 2007. [2] Alireza Vahdatpour, Majid Sarrafzadeh, Winston Wu, Lawrence Au, Brett Jordan, Thanos Stathopoulos, Maxim Batalin, William Kaiser, Meika Fang, and Joshua Chodosh, "The SmartCane System: An Assistive Device for Geriatrics," Third International Conference on Body Area Networks (BodyNets), Tempe, Arizona, March 2008. [3] Foad Dabiri, Alireza Vahdatpour, Hyduke Noshadi, Hagop Hagopian, and Majid Sarrafzadeh, "Ubiquitous Personal Assistive System for Neuropathy," The 2nd International Workshop on Systems and Networking Support for Healthcare and Assisted Living Environments (HealthNet), in conjunction with ACM MobiSys, Breckenridge, Colorado, July 2008. [4] S. Rohman, C. Santarelli, J.K. Pollard, M.E. Fry, A. Theodorou, and N. Mohoboob, "Wireless and web-based medical monitoring in the home," Medical Informatics and the Internet in Medicine, 27:217.219, 2002. [5] I. Neild, D. J T Heatley, R. S. Kalawsky, and P. A. Bowman, "Sensor networks for continuous health monitoring," BT Technology Journal, 22(3):130.139, 2004. =============================================================================== Paper Submission Deadlines: ---------------------------- BodyNets'09 - International Conference on Body Area Networks Los Angeles, CA Apr 1-3, 2009 Deadline: Nov 3, 2008 http://www.wirelesshealth.ucla.edu/bodynets/ SPL'09 - Southern Conference on Programmable Logic SãCarlos, Brazil Apr 1-3, 2009 Deadline: Nov 17, 2008 http://www.splconf.org/ ASYNC'09 - Intl. Symposium on Asynchronous Circuits and Systems Chapel Hill, NC May 17-20, 2009 Deadline: Dec 1, 2008 (abstracts due Nov 24) http://asyncsymposium.org DAC'09 - Design Automation Conference (sponsored by SIGDA) San Francisco, CA Jul 26-31, 2009 Deadline: Dec 19, 2008 http://www.dac.com/ FMGALS'09 - 4th International Workshop on Formal Methods for Globally Asynchronous and Locally Synchronous Designs Nice, France Apr 24, 2009 Deadline: Jan 9, 2009 http://memocode.irisa.fr/FMGALS09 SBCCI'09 - Symposium on Integrated Circuits and Systems Design Chip on the Dunes Natal, Brazil Aug 31 - Sep 3, 2009 Deadline: Mar 24, 2009 http://www.sbc.org.br/sbcci VLSI-SoC'09 - International Conference on Very Large Scale Integration Florianopolis, Brazil Oct 12-14, 2009 Deadline: Mar 28, 2009 http://www.inf.ufrgs.br/vlsisoc Edutech'09 Florianopolis, Brazil Oct 15-16, 2009 Deadline: Apr 30, 2009 http://www.inf.ufrgs.br/edutech ============================================================================== Upcoming Symposia, Conferences and Workshops: --------------------------------------------- VLSI-SoC'08 - Int'l Conference on Very Large Scale Integration Rhodes Island, Greece Oct 13-15, 2008 http://vlsi.ee.duth.gr/vlsisoc-2008/ CODES+ISSS'08 - Int'l Conference on Hardware-Software Codesign and System Synthesis (sponsored by SIGDA) Atlanta, GA Oct 19-24, 2008 http://www.codes-isss.org/ PACT'08 - Int'l Conference on Parallel Architectures and Compilation Techniques Toronto, Canada Oct 25-29, 2008 http://www.eecg.toronto.edu/pact/ ICCAD'08 - Int'l Conference on Computer-Aided Design (sponsored by SIGDA) San Jose, CA Nov 10-13, 2008 http://www.iccad.com/ MICRO'08 - Int'l Symposium on Microarchitecture Lake Como, Italy Nov 8-12, 2008 http://www.microarch.org/micro41/ ICPADS'08 - Int'l Conference on Parallel and Distributed Systems Melbourne, Australia Dec 8-10, 2008 http://www.deakin.edu.au/conferences/icpads2008/ EUC'08 - Int'l Conference on Embedded and Ubiquitous Computing Shanghai, China Dec 17-20, 2008 http://epcc.sjtu.edu.cn/euc2008/ HiPC'08 - Int'l Conference on High Performance Computing Bangalore, India Dec 17-20, 2008 http://www.hipc.org/ DFR'09 - Workshop on Design for Reliability (held in conjunction with the HiPEAC'09) Paphos, CYPRUS Jan 25, 2009 http://www.eng.ucy.ac.cy/theocharides/dfr09/index.htm HiPEAC'09 - Int'l Conference on High Performance Embedded Architectures & Compilers Paphos, Cyprus Jan 25-28, 2009 http://www.hipeac.net/conference ============================================================================== Call For Papers ---------------- IEEE Design and Test Special Issue on 3D IC Design and Test of Computers September/October 2009 Guest Editors: David Kung (IBM Research) and Yuan Xie (Pennsylvania State University) 3D integration is emerging as an attractive way to sustain Moore's law and even to enable more than Moore. The key benefits of 3D ICs over traditional 2D chips include reduction of the global interconnect length, higher packing density, smaller footprint, and the enablement of mixed-technology integration. Design and test techniques and methodologies for 3D designs are imperative for 3D integration. Novel architectures and design space exploration at the architectural level are also essential to leveraging 3D integration technologies for performance gain. IEEE Design & Test seeks original manuscripts for a special issue on 3D IC Design and Test, scheduled for publication in September/October 2009. Topics of interest include, but are not limited to the following: . Novel architectural-level design, such as nonvolatile memory stacking and 3D networks on chips (NoCs) . Architectural- and physical-level design automation algorithms and tools . Thermal analysis methods and thermal-aware design techniques for 3D ICs . Cost and yield analysis for 3D ICs . Testing techniques for 3D ICs, such as scan chain design, test-access mechanisms, and known-good-die (KGD) testing Submission and review procedures Prospective authors should follow the submission guidelines for IEEE Design & Test. All manuscripts must be submitted electronically to the IEEE Manuscript Central Web site at https://mc.manuscriptcentral.com/cs-ieee. Indicate that you are submitting your article to the special issue on "3D IC Design and Test." All articles will undergo the standard IEEE Design & Test review process. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere. Manuscripts must not exceed 5,000 words, including figures (with each average-size figure counting as 150 words) and including a maximum of 12 References (50 for surveys). This amounts to about 4,200 words of text and a maximum of five small to medium figures. Accepted articles will be edited for clarity, structure, conciseness, grammar, passive to active voice, logical organization, readability, and adherence to style. Please see IEEE Design & Test Author Resources at http://www.computer.org/dt/author.htm, then scroll down and click on Author Center for submission guidelines and requirements. Deadlines . Submissions deadline: 20 December 2008 . Reviews completed: 20 February 2009 . Revisions (if required) due: 20 March 2009 . Notification of final acceptance: 10 April 2009 . Submission of final version: 15 June 2009 Questions? Please direct questions regarding this special issue to Guest Editors David Kung (kung@us.ibm.com) and Yuan Xie (yuanxie@cse.psu.edu). ============================================================================== Call For Papers ---------------- NOCS 2009: THE 3RD ACM*/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP May 10-13, 2009, San Diego, CA http://circuit.ucsd.edu/~nocs2009/ IMPORTANT DATES: Abstract deadline: January 23, 2009 (hard deadline) Full paper deadline: January 30, 2009 (hard deadline) Proposals for tutorials, special sessions, and panels: January 30, 2009 Notification of acceptance: March 13, 2009 NOCS is the premier event dedicated to research on on-chip communication technology, architecture, design methods and applications. Original papers describing new and previously unpublished results are solicited on all aspects of NoC technology. Topics of interest include, but are not limited to: - Network architecture (topology, routing, arbitration, ...) - Network design for 3D stacked logic and memory - Mapping of applications onto NoCs - Power and energy issues - Timing, synchronous/asynchronous communication - NoC reliability issues - O/S support for NoCs - Metrics and benchmarks for NoCs - Multi/many-core workload characterization & evaluation - NoC network interface issues - Modeling, simulation, and synthesis of NoCs - NoC support for memory and cache access - NoC design methodologies and tools - NoC Quality of Service - NoCs for FPGAs and structured ASICs - NoC support for CMP/MPSoCs - Novel interconnect links/switches/routers - Optical & RF for on-chip/in-package interconnects - Signaling and circuit design for NoC links - Physical design of interconnect and NoC - Floorplan-aware NoC architecture optimization - Verification, debug & test of NoC - NoC case studies, application-specific NoC design - Programming models Electronic paper submission requires a full paper, up to 10 double-column IEEE format pages, including figures and references. Papers will be evaluated by the program committee in a blind review process based on scientific merit, innovation, relevance, and presentation. Proposals for tutorial papers and panel sessions are also invited. A special section related to the theme of the conference will be organized in collaboration with the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Organizing Committee: * General Chairs: Bill Lin (UCSD), Partha Kundu (Intel) * Program Chairs: Radu Marculescu (CMU), Axel Jantsch (KTH, Sweden) * Finance Chair: Karam Chatha (Arizona State) * Registration Chair: Joerg Henkel (U. Karlsruhe, Germany) * Publications Chair: Luca Carloni (Columbia) * Publicity Chair: Davide Bertozzi (U. Ferrara, Italy) * Tutorials Chair: Kees Goossens (NXP & TU Delft, Netherlands) Sponsored by IEEE CAS/CEDA & ACM SIGARCH/SIGBED/SIGDA *ACM sponsorship pending ============================================================================== Call for Papers ---------------------------------- TAU 2009 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems http://www.tauworkshop.com February 23-24, 2009 Lakeway Resort, Austin, Texas Sponsored by ACM/SIGDA and IEEE/CAS The TAU series of workshops provide an informal forum for practitioners and researchers working on temporal aspects of digital systems to disseminate early work and engage in a free discussion of ideas. The sixteenth in the TAU series, the TAU 2009 workshop invites submissions from all areas related to the timing properties of digital electronic systems, including but not limited to: Topics: Formal theories and methods System-level timing Transistor-level timing Circuit-level timing Sensitivity analysis Full custom design analysis Integrated functional-temporal analysis Incremental analysis Timing issues in low power design Power-delay trade-offs Adjacent line switching and coupling Delay models and metrics Layout impact on timing Timing-driven layout optimization Timing-driven synthesis and re-synthesis Circuit optimization Uncertainty-based analysis Incorporation of RETs in timing Reliability impact on performance Process & environmental variation models Statistical analysis techniques Clocking, synchronization, and skew Clock domains, static/dynamic logic Novel clocking schemes Special circuit families Asynchronous systems Timing implications of emerging technologies IMPORTANT DATES Submission deadline December 22, 2008 Acceptance notification January 26, 2009 Camera-ready paper due February 5, 2009 SUBMISSION OF PAPERS All papers must be submitted electronically. Details will be posted on the web site http://www.tauworkshop.com. Submissions are limited to 6 pages in the double column proceedings format. TAU is a workshop aimed at fostering a high level of professional interaction, not a conference. Copies of papers will be provided to the attendees, but the proceedings will not be published by the ACM or the IEEE. Therefore, accepted papers can still be submitted to other conferences and journals. The intent of the workshop is to encourage the vigorous and unfettered discussion of the latest ideas in the field. WORKSHOP ORGANIZATION: General Chair: Frank Liu, IBM Corporation Program Chair: Peng Li, Texas A&M University ============================================================================== Call For Papers ----------------- DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Test - Palais des CongrèAcropolis - Nice, France Friday April 24, 2009 http://www.date-conference.com/ INTRODUCTION The Design, Automation, and Test in Europe (DATE) conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in hardware and software design, test and manufacturing of electronic circuits and systems. The conference includes plenary invited papers, regular papers, panels, hot-topic sessions, tutorials and workshops, two special focus days, and a track for executives. Friday Workshops are focusing on emerging research and application topics. At DATE 2009, one of the Friday Workshops is devoted to 3D Integration. This one-day event consists of a plenary keynote, regular and poster presentations, and a panel session. WORKSHOP DESCRIPTION 3D Integration is a promising technology for extending Moore's momentum in the next decennium, offering higher transistor density, faster interconnects, heterogeneous technology integration, and potentially lower cost and time-tomarket. But before 3D chips can be produced, new capabilities are needed: process technology, architectures, design methods and tools, and manufacturing test solutions. The goal of this Workshop is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges. TOPIC AREAS You are invited to participate and submit your contributions to the DATE 2009 Friday Workshop on 3D Integration. The area of interest includes (but is not limited to) the following topics: . 3D technologies: wire-bonding, micro-bumping, contactless, and through-silicon-vias interconnect . 3D design space exploration . Architectures for 3D integration . 3D combinations of logic, memory, analog, RF . 3D design methods and EDA tools . Signal integrity and noise coupling in 3D . Thermal analysis and thermal-aware design . Test, design-for-test, and debug techniques . Product or test chip case studies . Economic benefit/cost trade-off studies . Standardization initiatives Submissions are invited in the form of (extended) abstracts not exceeding two pages and must be sent in as PDF file to and with "DATE09-3D-WS" as subject. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, and technical soundness. Selected submissions can be accepted for regular or poster presentation. At the workshop, an Electronic Workshop Digest will be made available to all workshop participants, which will include all material that authors are willing to provide: abstract, paper, slides, poster, etc. Paper Submission deadline : November 8, 2008 Notification of Acceptance : November 17, 2008 Camera-Ready Material due date: April 10, 2009 MORE INFORMATION Erik Jan Marinissen - General Chair IMEC Nomadic Embedded Systems Kapeldreef 75 3001 Leuven, Belgium E-mail: erik.jan.marinissen@imec.be Yann Guillou - Program Co-Chair ST-NXP Wireless Wireless Multimedia Division 12, rue Jules Horowitz - BP 217 38019 Grenoble cedex, France E-mail: yann.guillou@stnwireless.com Geert Van der Plas - Program Co-Chair IMEC Nomadic Embedded Systems Kapeldreef 75 3001 Leuven, Belgium E-mail: geert.vanderplas@imec.be ============================================================================== Upcoming Funding Opportunities ---------------------------------- DARPA Strategic Technologies (BAA 08-10) Deadline: February, 2009 http://www.darpa.mil/sto/solicitations/BAA08-10/index.html DOD SPINS in Semiconductors Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Artificial Intelligence Technologies Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Quantum Information Science and Technology Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Microsystems Technology Office-Wide Deadline: January 14, 2009 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html Modeling and Simulation for Information Systems Research Deadline: FY 10 should be submitted by June 1, 2009 http://fedbizopps.cos.com/cgi-bin/getRec?id=20061030a9 Test and Evaluation Deadline: July 2009 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Cognition and Neuroergonomics Collaborative Technology Alliance (CTA) - W911NF-08-R-0014 Deadline: July 01, 2009 http://fedbizopps.cos.com/cgi-bin/getRec?id=20080811a12 Cognitive Neuroscience (CNS) or Other Emerging or Leap-Ahead Technologies That Offer to Dramatically Advance Submarine Sonar or Other Advanced Underwater Systems Deadline: July 2009 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Information Warfare: Offensive and Defensive Counterinformation - BAA-06-12-IFKA Deadline: Continuous until December 2009 https://www.fbo.gov/index?s=opportunity&mode=form&id=5a4214baae590a1808f3077a0e7b9244&tab=core&_cview=1 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.rdecom.army.mil/STTC/2006_N61339-05-R-0095__BAA_FY06_Amendment_0001.pdf Army Research Office (ARO) Broad Agency Announcement for Basic and Applied Scientific Research (W911NF-07-R-0003) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 ARL/ARO Core Broad Agency Announcement for Basic and Applied Scientific Research for Fiscal Years 2007 through 2011 (W911NF-07-R-0001) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 Systems and Software (AFOSR-BAA-2008-1) Deadline: Continuous http://www.wpafb.af.mil/shared/media/document/AFD-080212-048.pdf NSF Collaborative Research in Computational Neuroscience (CRCNS) Deadline: February 26, 2008 October 30, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=5147&org=CISE&from=home Accelerating Discovery in Science and Engineering Through Petascale Simulations and Analysis (PetaApps) - NSF 08-592 Deadline: October 30, 2008 http://www.nsf.gov/pubs/2008/nsf08592/nsf08592.htm TeraGrid Phase III: eXtreme Digital Resources for Science and Engineering (XD) Deadline: November 04, 2008 http://www.nsf.gov/pubs/2008/nsf08571/nsf08571.htm High Performance Computing Acquisition: Towards a Petascale Computing Environment for Science and Engineering - NSF 05-625 Deadline: November 28, 2008 http://www.nsf.gov/pubs/2005/nsf05625/nsf05625.htm Information and Intelligent Systems (IIS): Core Programs Deadline: Medium Projects October 1, 2008 - October 31, 2008 Large Projects November 1, 2008 - November 28, 2008 Small Projects December 1, 2008 - December 17, 2008 http://www.nsf.gov/div/index.jsp?div=IIS Computing and Communication Foundations (CCF): Core Programs Deadline: Medium Projects October 1, 2008 - October 31, 2008 Large Projects November 1, 2008 - November 28, 2008 Small Projects December 1, 2008 - December 17, 2008 http://www.nsf.gov/pubs/2008/nsf08577/nsf08577.htm#pgm_desc_txt USDA Electronics/Computer Engineer - RA-08-065H (postdoctoral opportunity) Deadline: Continuous http://www.afm.ars.usda.gov/divisions/hrd/hrdhomepage/vacancy/08065.htm DOE Lawrence Fellowship Deadline: November 03, 2008 https://fellowship.llnl.gov/ Sigma Delta Epsilon/Graduate Women in Science, Inc. Sigma Delta Epsilon (SDE) Fellowships Deadline: January 15, 2009 http://www.gwis.org/grants/default.htm ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. 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