=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membership. Circulation: 2,700 =============================================================================== 1 October 2008 ACM/SIGDA E-NEWSLETTER Vol. 38, No. 19 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Soheil Ghiasi Contributing author: Matthew Guthaus Contributing author: Umit Y Ogras Contributing author: Marc Riedel Contributing author: Lin Yuan (2) What Is Majority/Minority Network Synthesis? Contributing author: Niraj K. Jha, Princeton University From: Deming Chen (3) Paper Submission Deadlines From: Debjit Sinha (4) Upcoming Conferences and Symposia From: Debjit Sinha (5) Upcoming Funding Opportunities From: Qinru Qiu (6) Call for Participation - IEEE/ACM Compact Variability Workshop From: Frank Liu (7) Call for Nominations: 2008 Computer-Aided Verification (CAV) Award From: Aarti Gupta (8) Call for Papers: 7th ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE) From: Patrick Schaumont (9) GLSVLSI 2009 Call for Papers From: David Atienza Alonso =============================================================================== Dear ACM/SIGDA members, In this issue, we have reprinted the "What Is ..." column from Prof. Niraj K. Jha of Princeton University. Our target is to publish a new and original "What Is ..." column every month. We welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Qing Wu, E-Newsletter Editor; Matthew Guthaus, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Debjit Sinha, E-Newsletter Associate Editor; Lin Yuan, E-Newsletter Associate Editor; Soheil Ghiasi, E-Newsletter Associate Editor; Deming Chen, E-Newsletter Associate Editor; Umit Ogras, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "Automotive EEPROMs Use Two Cells Per Bit For Ruggedness, Reliability" http://www.edn.com/article/CA6598379.html?industryid=47037 With the aim of ensuring reliable operation and long life in the demanding automotive environment, Rohm has introduced a series of EEPROMs that employ a double-cell structure. The BR25Hxx0 devices, which are SPI (serial-peripheral-interface)-bus memories, withstand the voltage surges, static discharge, heat, and vibration that they may encounter in automotive ECUs (engine-control units). Features include guaranteed operation at 125°C, with 20-year data retention at 85°C, 6-kV ESD (electrostatic-discharge) resistance, gold-pad/gold-wire connections, and a double-reset function for high reliability. The devices' high-redundancy circuits and a choice of process technology allow the company to specify a life of 1 million rewrites at 85°C and 300,000 rewrites at 125°C "TSMC Pushes Out High-K in 28-nm Rollout" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210604347 Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has rolled out its 28-nm process and revealed a surprise: It has pushed out--or delayed--its initial high-k/metal-gate offering until 28-nm, putting it slightly behind its rivals in Chartered, IBM and Samsung. TSMC was originally supposed to have its high-k/metal-gate offering at the 32-nm node. "New Biosolar Processes Could Halve Solar Cells Cost" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210604733 BioSolar, Inc., the developer of a technology to produce bio-based materials from renewable plant sources that reduce the cost of solar cells, has announced a new technique that can potentially reduce the cost of its BioBacksheet product by up to 50%. "Measuring Quality In Semiconductor IP" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210604484 Semiconductor IP reuse can yield a 2x improvement in design productivity for semiconductor companies. However, with these startling productivity gains come integration pain. Why? Semiconductor IP is essentially a black box for the SoC team that comes from various external sources, with varying and often unknown levels of quality and reusability. SoC designers must find a quality metric for semiconductor IP. If not, they may abandon its use. "Intel, IBM Explore Co-Polymer Lithography" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210604208 Several entities, including IBM Corp. and Intel Corp., are exploring a new technology called co-polymer lithography in an effort to extend Moore's Law. "Advanced Technology Week in Review: MEMS, and More MEMS" http://www.eetimes.com/showArticle.jhtml?articleID=210604206 A new MEMS microphone design and a thinner MEMS oscillator along with electronic-paper tablets and a new spherical design for a ultrawideband antenna highlight this week's technology review. "Opinion: Time to Panic?" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210602439 As I write this, the Dow Jones Industrial Average is off by 800 points since Monday's opening-a roughly 6% drop in two days. If that doesn't scare you, consider that the index has dropped a stunning 25% in the last year. Things are even worse in other markets. Russia halted trading after the market fell by 10% in a single hour. The Chinese market has lost 2/3 of its value. Still not worried? In parts of the US, home prices are down 34% from last year. Major banks and insurers are failing. A major money market fund has frozen all accounts as it suffers huge losses. Need I go on? "Synopsys Officially Enters Analog/Mixed-Signal EDA Market" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210603165 As expected, EDA vendor Synopsys Inc. officially expanded into the realm of analog/mixed-signal design tools with the introduction Monday (Sept. 22) of Galaxy Custom Designer. "Americans Ignorant of Plans to Create Artificial Life" http://www.foxnews.com/story/0,2933,431401,00.html If you've never heard of the exciting field of synthetic biology, you're not alone, but you might want to get wise to the field's controversial promise to create life from scratch. "Is Algorithmic Synthesis the One True ESL Path? A Clue: No" http://www.edn.com/index.asp?layout=blog&blog_id=980000298&blog_post_id=680033468 Leibson's Law: It takes 10 years for any disruptive technology to become pervasive in the design community. This blog is about the disruptive technologies that either have or will win over electronic engineers, some that won't, and why. Written by Steve Leibson, Tensilica's Technology Evangelist. See my history site at www.hp9825.com. "EDA Tools Aid In Drug Design" http://www.eetindia.co.in/ART_8800503783_1800000_NT_62d1272f.HTM EDA industry veterans say techniques used for chip design can be adopted for new drug discovery and development. "An Open Source Legal Breakthrough" http://tech.slashdot.org/article.pl?sid=08/10/03/1447248 An appeals court case (Jacobsen vs Katzer) has confirmed the validity of Open Source licensing such as GNU, Creative Commons, etc. The case involves open source IP that was used in a proprietary application without following the license agreement. ============================================================================== What Is Majority/Minority Network Synthesis? ---------------------------- Niraj K. Jha, Department of Electrical Engineering, Princeton University Majority (minority) network synthesis uses majority (minority) gates as logic elements. A majority (minority) gate has three inputs and one output and produces an output value 1 when a majority (minority) of input values are 1. Thus, the majority function, M, corresponding to a majority gate is given by M(x1,x2,x3) = x1x2 + x2x3 + x1x3 The minority function, m, is simply given by M' (the complement of M). Majority/minority gates are the basic logic primitives in various nanotechnologies, such as quantum cellular automata (QCA), single-electron box (SEB), and tunneling phase logic (TPL). This has revived interest in majority/minority network synthesis. By tying one of its inputs to 0 (1), a majority gate can implement an AND (OR) gate, respectively. Thus, a majority gate along with an inverter form a functionally complete set of logic elements. Similarly, just the minority gate is functionally complete. However, such a use of a majority (minority) gate, i.e., tying one of its inputs to a 0 to obtain an AND (NAND) gate or a 1 to obtain an OR (NOR) gate, is a very sub-optimal use of such a gate. In other words, first performing traditional logic synthesis using AND and OR gates and then replacing them with majority gates with an input tied to a constant is likely to result in a majority network that requires many more majority gates than would be needed when direct majority network synthesis is performed in which all three inputs of the majority gates are made use of. Since a minority network can be very simply obtained from a majority network with the help of De Morgan's theorem, it is sufficient for the logic synthesis algorithm to just target majority network synthesis. Although the 60's and 70's saw some work on majority network synthesis [1], a general multi-level majority network synthesis algorithm was never developed. Such an algorithm is presented in ref. [2]. It has interesting parallels with traditional logic synthesis. For example, traditional two-level logic synthesis implements a sum of a subset of prime implicants. Two-level majority logic synthesis uses realizable patterns, instead of prime implicants, as building blocks. A realizable pattern is a pattern of 1 cells in a three-input Karnaugh map that can be implemented with one majority gate. There are 38 such patterns. For multi-level majority network synthesis, each logic node can be synthesized with the help of realizable patterns. [1] S. Muroga, Threshold Logic and its Applications, John Wiley, New York, NY, 1971. [2] R. Zhang, P. Gupta, and N. K. Jha, "Majority and minority network synthesis with application to QCA, SET and TPL based nanotechnologies," IEEE Transactions on Computer-Aided Design, vol. 26, July 2007. ============================================================================== Paper Submission Deadlines: ---------------------------- ISPD'09 - Int'l Symposium on Physical Design (sponsored by SIGDA) San Diego, CA Mar 29 - Apr 1, 2009 Deadline: Oct 5, 2008 http://www.ispd.cc/ ISCAS'09 - Int'l Symposium on Circuits and Systems Taipei, Taiwan May 24-27, 2009 Deadline: Oct 10, 2008 http://iscas2009.org/ ISQED'09 - Int'l Symposium on Quality Electronic San Jose, CA Mar 16-18, 2008 Deadline: Oct 10, 2008 http://www.isqed.org/ SPL'09 - Southern Conference on Programmable Logic SãCarlos, Brazil Apr 1-3, 2009 Deadline: Nov 17, 2008 http://www.splconf.org/ ASYNC'09 - Intl. Symposium on Asynchronous Circuits and Systems Chapel Hill, NC May 17-20, 2009 Deadline: Dec 1, 2008 (abstracts due Nov 24) http://asyncsymposium.org DAC'09 - Design Automation Conference (sponsored by SIGDA) San Francisco, CA Jul 26-31, 2009 Deadline: Dec 19, 2008 http://www.dac.com/ FMGALS'09 - 4th International Workshop on Formal Methods for Globally Asynchronous and Locally Synchronous Designs Nice, France Apr 24, 2009 Deadline: Jan 9, 2009 http://memocode.irisa.fr/FMGALS09 SBCCI'09 - Symposium on Integrated Circuits and Systems Design Chip on the Dunes Natal, Brazil Aug 31 - Sep 3, 2009 Deadline: Mar 24, 2009 http://www.sbc.org.br/sbcci VLSI-SoC'09 - International Conference on Very Large Scale Integration Florianopolis, Brazil Oct 12-14, 2009 Deadline: Mar 28, 2009 http://www.inf.ufrgs.br/vlsisoc Edutech'09 Florianopolis, Brazil Oct 15-16, 2009 Deadline: Apr 30, 2009 http://www.inf.ufrgs.br/edutech ============================================================================== Upcoming Symposia, Conferences and Workshops: --------------------------------------------- VLSI-SoC'08 - Int'l Conference on Very Large Scale Integration Rhodes Island, Greece Oct 13-15, 2008 http://vlsi.ee.duth.gr/vlsisoc-2008/ CODES+ISSS'08 - Int'l Conference on Hardware-Software Codesign and System Synthesis (sponsored by SIGDA) Atlanta, GA Oct 19-24, 2008 http://www.codes-isss.org/ PACT'08 - Int'l Conference on Parallel Architectures and Compilation Techniques Toronto, Canada Oct 25-29, 2008 http://www.eecg.toronto.edu/pact/ ICCAD'08 - Int'l Conference on Computer-Aided Design (sponsored by SIGDA) San Jose, CA Nov 10-13, 2008 http://www.iccad.com/ MICRO'08 - Int'l Symposium on Microarchitecture Lake Como, Italy Nov 8-12, 2008 http://www.microarch.org/micro41/ ICPADS'08 - Int'l Conference on Parallel and Distributed Systems Melbourne, Australia Dec 8-10, 2008 http://www.deakin.edu.au/conferences/icpads2008/ EUC'08 - Int'l Conference on Embedded and Ubiquitous Computing Shanghai, China Dec 17-20, 2008 http://epcc.sjtu.edu.cn/euc2008/ HiPC'08 - Int'l Conference on High Performance Computing Bangalore, India Dec 17-20, 2008 http://www.hipc.org/ DFR.09 - Workshop on Design for Reliability (held in conjunction with the HiPEAC'09) Paphos, CYPRUS Jan 25, 2009 http://www.eng.ucy.ac.cy/theocharides/dfr09/index.htm HiPEAC'09: Int'l Conference on High Performance Embedded Architectures & Compilers Paphos, Cyprus Jan 25-28, 2009 http://www.hipeac.net/conference ============================================================================== Upcoming Funding Opportunities ---------------------------------- DARPA Strategic Technologies (BAA 08-10) Deadline: February, 2009 http://www.darpa.mil/sto/solicitations/BAA08-10/index.html DOE Advanced Scientific Computing Research (ASCR) (DE-PS02-08ER08-01) Deadline: September 30, 2008 http://www.science.doe.gov/grants/FAPN08-01.html DOD Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html SPINS in Semiconductors Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Artificial Intelligence Technologies Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Quantum Information Science and Technology Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Microsystems Technology Office-Wide Deadline: January 14, 2009 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html Modeling and Simulation for Information Systems Research Deadline: FY 10 should be submitted by June 1, 2009 http://fedbizopps.cos.com/cgi-bin/getRec?id=20061030a9 Test and Evaluation Deadline: July 2009 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Cognition and Neuroergonomics Collaborative Technology Alliance (CTA) - W911NF-08-R-0014 Deadline: July 01, 2009 http://fedbizopps.cos.com/cgi-bin/getRec?id=20080811a12 Cognitive Neuroscience (CNS) or Other Emerging or Leap-Ahead Technologies That Offer to Dramatically Advance Submarine Sonar or Other Advanced Underwater Systems Deadline: July 2009 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Information Warfare: Offensive and Defensive Counterinformation - BAA-06-12-IFKA Deadline: Continuous until December 2009 https://www.fbo.gov/index?s=opportunity&mode=form&id=5a4214baae590a1808f3077a0e7b9244&tab=core&_cview=1 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.rdecom.army.mil/STTC/2006_N61339-05-R-0095__BAA_FY06_Amendment_0001.pdf Army Research Office (ARO) Broad Agency Announcement for Basic and Applied Scientific Research (W911NF-07-R-0003) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 ARL/ARO Core Broad Agency Announcement for Basic and Applied Scientific Research for Fiscal Years 2007 through 2011 (W911NF-07-R-0001) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 Systems and Software (AFOSR-BAA-2008-1) Deadline: Continuous http://www.wpafb.af.mil/shared/media/document/AFD-080212-048.pdf NSF CreativeIT - NSF 08-572 Deadline: September 26, 2008 http://www.nsf.gov/pubs/2008/nsf08572/nsf08572.htm Engineering Design and Innovation (EDI) Deadline: October 1, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13340 Multicore Chip Design and Architecture: (MCDA) - NSF 08-584 Deadline: October 17, 2008 http://www.nsf.gov/pubs/2008/nsf08584/nsf08584.htm Collaborative Research in Computational Neuroscience (CRCNS) Deadline: February 26, 2008 October 30, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=5147&org=CISE&from=home Accelerating Discovery in Science and Engineering Through Petascale Simulations and Analysis (PetaApps) - NSF 08-592 Deadline: October 30, 2008 http://www.nsf.gov/pubs/2008/nsf08592/nsf08592.htm TeraGrid Phase III: eXtreme Digital Resources for Science and Engineering (XD) Deadline: November 04, 2008 http://www.nsf.gov/pubs/2008/nsf08571/nsf08571.htm High Performance Computing Acquisition: Towards a Petascale Computing Environment for Science and Engineering - NSF 05-625 Deadline: November 28, 2008 http://www.nsf.gov/pubs/2005/nsf05625/nsf05625.htm Information and Intelligent Systems (IIS): Core Programs Deadline: Medium Projects October 1, 2008 - October 31, 2008 Large Projects November 1, 2008 - November 28, 2008 Small Projects December 1, 2008 - December 17, 2008 http://www.nsf.gov/div/index.jsp?div=IIS Computing and Communication Foundations (CCF): Core Programs Deadline: Medium Projects October 1, 2008 - October 31, 2008 Large Projects November 1, 2008 - November 28, 2008 Small Projects December 1, 2008 - December 17, 2008 http://www.nsf.gov/pubs/2008/nsf08577/nsf08577.htm#pgm_desc_txt USDA Electronics/Computer Engineer - RA-08-065H (postdoctoral opportunity) Deadline: Continuous http://www.afm.ars.usda.gov/divisions/hrd/hrdhomepage/vacancy/08065.htm Microsoft Microsoft Research and Live Labs Ph.D. Fellowship Deadline: October 17, 2008 http://research.microsoft.com/aboutmsr/jobs/fellowships/apply_us.aspx DOE Lawrence Fellowship Deadline: November 03, 2008 https://fellowship.llnl.gov/ Sigma Delta Epsilon/Graduate Women in Science, Inc. Sigma Delta Epsilon (SDE) Fellowships Deadline: January 15, 2009 http://www.gwis.org/grants/default.htm ============================================================================== Call for Participation --------------------------- IEEE/ACM Compact Variability Workshop Time: November 13, 2008 (Collocated with 2008 ICCAD) Location: Double-tree Hotel, San Jose, CA, USA It is widely recognized that process variation is emerging as a fundamental challenge to IC design with scaled CMOS technology; and that it will have profound impact on nearly all aspects of circuit performance. While some of the negative effects of variability can be handled with improvements in the manufacturing process, the industry is starting to accept the fact that some of the effects are better mitigated during the design process. Handling variability in the design process will require accurate and appropriate models of variability and its dependence on designable parameters (i.e. layout), and its spatial and temporal distribution. Such models are quite different from the .corner. models deployed thus far to model manufacturing variability. As a consequence, the compact modeling of systematic, spatial, and random variations is essential to abstract the physical level variations into a format the designers (and .importantly- the tools that they use) can utilize. In this IEEE and ACM sponsored workshop, nine outstanding speakers from both industry and academia are invited to provide a comprehensive overview of the current practices. It is also the intention of this workshop to provide a forum to discuss future trends and research needs. Advance Program: 8:25 - 8:30am Opening Remarks 8:30 - 9:50am Session I: The Needs of Variational Compact Models Luigi Capodieci (AMD): Managed Variability: Present and Future of Design-Process Integration from 45nm, and 32nm, to 22nm and Beyond Samar Saha (SilTerra): Variability in Scaled CMOS Technology and Modeling Approaches for Circuit Simulation 9:50 - 10:20am Morning Break/Discussion 10:20 - 11:40am Session II: Current Statistical Device Model Colin McAndrew (Freescale): Backward Propagation of Variance: You Measure it, BPV can Model it! John Krick (TI): Statistical Transistor SPICE Modeling in Advanced CMOS Technologies 11:40 - 1:00pm Lunch 1:00 - 3:00pm Session III: Practice on Variation Modeling Chenming Hu (UC Berkeley): Compact Models of Some MOSFET Variations Joe Watts (IBM): A Multilevel Approach to Statistical Compact Modeling Xi-Wei Lin (Synopsys): Modeling of Proximity Effects in Nanometer MOSFET 3:00 - 3:30pm Afternoon Break/Discussion 3:30 - 4:50pm Session IV: Statistical Characterization and Simulation Bruce McGaughy (ProPlus Design): Model Extraction and Simulation Challenges for Process Variations in 45nm and Below Kishore Singhal (Synopsys): Display and Analysis of Variability Simulation Results 4:50 - 5:10pm Closing Remarks The workshop is co-sponsored by ACM SIGDA and IEEE EDS, with additional support from SRC and IBM Corp. Workshop Organizers: Frank Liu, IBM Yu (Kevin) Cao, Arizona State Univeristy For more details, please visit workshop webpage: http://www.eas.asu.edu/~ycao/cvm/. To register for the workshop, please visit ICCAD website http://www.iccad.com. The advanced registration with discount rate ends on Oct 18, 2008. ============================================================================== Call for Nominations ---------------------- 2008 Computer-Aided Verification (CAV) Award http://www.princeton.edu/cav2008 An annual award, called the CAV Award, has been established "For a specific fundamental contribution or a series of outstanding contributions to the field of Computer-Aided Verification." The cited contribution(s) must have been made not more recently than five years ago and not over twenty years ago. In addition, the contribution(s) should not yet have received recognition via a major award, such as the ACM Turing or Kanellakis Awards. The award of $10,000 will be granted to an individual or a group of individuals chosen by the Award Committee from a list of nominations. The Award Committee may choose to make no award in a given year. The CAV Award will be presented in an award ceremony at the Computer-Aided Verification Conference and a citation will be published in a journal of record (currently, Formal Methods in System Design). Anyone, with the exception of members of the Award Committee, is eligible to receive the Award. Anyone can submit a nomination except a member of the Steering Committee of the Computer-Aided Verification Conference, or someone whose term of service on the Award Committee ended within the last two years. The Award Committee can originate a nomination. A nomination must state clearly the contribution(s), explain why the contribution is fundamental or the series of contributions is outstanding, and be accompanied by supporting letters and other evidence of worthiness. Nominations should include a proposed citation (up to 25 words), a succinct (100-250 words) description of the contribution(s), and a detailed statement to justify the nomination. For the CAV Award in 2008, please send nominations to one of the following two Steering Committee members of the Computer-Aided Verification Conference, who will forward the nominations to the Chair of the Award Committee: * Edmund M. Clarke, CMU, emc@cs.cmu.edu * Robert P. Kurshan, Cadence, rkurshan@cadence.com Nominations must be received by January 28, 2008. ============================================================================== Call for Papers -------------------- Seventh ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE) http://csg.csail.mit.edu/Memocode2009/ 13-15 July 2009, Cambridge, Massachusetts, USA The seventh MEMOCODE conference will gather researchers and practitioners who create methods, tools, and architectures for hardware/software systems. Modern design faces increased design complexities in combination with tightening implementation constraints. This requires new techniques to create, refine, and verify hardware/software systems. MEMOCODE seeks submissions that present novel formal methods and design techniques to address this design problem. We also invite application-oriented papers, and especially encourage submissions that highlight the design perspective of formal methods and models, including success stories and demonstrations of hardware/software codesign. Furthermore, we invite poster presentations describing ongoing work with promising preliminary results. Submission topics include, but are not limited to 1. System-level modeling and verification, abstraction and refinement between different modeling levels, formal, semi-formal, and specification-driven verification on the system level. Transaction-level modeling. 2. Design and verification methods for composition of concurrent systems: Multi-core architectures, networks-on-chip. 3. Non-traditional and domain-specific design languages for hardware and software, novel models of computation, and new design paradigms that unify hardware and software design. 4. System-level estimation of performance and power in heterogeneous hardware/software architectures. 5. Applications and demonstrators of formal design methodologies and case studies of innovative system-level design flows. 6. Modeling and reuse of intellectual property at system-level. IMPORTANT DATES Paper submission 20 February 2009 Notification of acceptance 8 May 2009 Poster submission 15 May 2009 Notification for posters 29 May 2009 Final Version of Papers 29 May 2009 DESIGN CONTEST MEMOCODE will again have a design contest. The contest will start 1 March 2009. The deadline for submission is 31 March 2009 and the notification of the results is on 8 May 2009. The conference will sponsor at least two prize categories, each with a significant cash award. We awarded a $1000 prize in each of the three categories in 2008. Each team that submits a complete and working entry will be invited to submit for review a 2-page abstract for the formal conference proceedings; prize winning teams will be invited to contribute a 4-page short paper. Please refer to the conference website for more information and updates. PROCEEDINGS Conference proceedings will be published by the IEEE Computer Society. The best papers will be considered for a special issues of a major journal. SUBMISSION Submissions of research and experience papers will only be accepted through the conference web site. Papers must not exceed 10 pages and must be formatted following IEEE Computer Society guidelines. Submissions must be written in English, describe original work, and not substantially overlap papers that have been published or are being submitted to a journal or another conference with published proceedings. Posters submissions should consist of an abstract of at most 250 words. The abstract will be distributed to the conference attendants, but will not be published. Note that the poster deadline is different from the paper deadline. ORGANIZATION General chairs: Rajesh Gupta and James C. Hoe Design contest chairs: Forrest Brewer and James C. Hoe Local chair: Sally Lee Program committee chairs: Roderick Bloem and Patrick Schaumont PROGRAM COMMITTEE Clark Barrett New York University Twan Basten Eindhoven University of Technology Tevfik Bultan University of California, Santa Barbara Luca Carloni Columbia University Rainer Doemer University of California, Irvine Robert de Simone INRIA Rolf Drechsler University of Bremen Stephen A. Edwards Columbia Univeristy Franco Fummi University of Verona David Hwang George Mason University Ganesh Gopalakrishnan University of Utah Barbara Jobstmann EPFL Daniel Kroening Oxford University Luciano Lavagno Politecnico di Torino Elizabeth Leonard NRL John O'Leary Intel Klaus Schneider University of Kaiserslautern Satnam Singh Microsoft Research Frank Vahid University of California, Riverside Kazutoshi Wakabayashi NEC Reinhard Wilhelm Saarland University Fei Xie Portland State University ============================================================================== GLSVLSI 2009 Call for Papers ------------------------------- IEEE/ACM GSLVSLI 2009 19th Great Lakes Symposium on VLSI Systems May 10-12, 2008, Boston, Massachusetts, USA http://www.glsvlsi.org/ ABOUT GLSVLSI: The 19th edition of GLSVLSI will be held in Boston, Massachusetts. Original, unpublished papers, describing research in the general area of VLSI are solicited. Both theoretical and experimental research results are welcome. Proceedings will be published by the ACM and will be available through the ACM Digital Library and IEEE Xplore. For detailed information, visit http://glsvlsi.org/. PROGRAM TRACKS: 1. VLSI Design: design of ASICs, microprocessors/micro-architectures, embedded processors, analog/digital/mixed-signal systems, NoC, interconnects, memories, and FPGAs. 2. VLSI Circuits: analog/digital/mixed-signal circuits, RF and communication circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits, arithmetic circuits. 3. Computer-Aided Design (CAD): hardware/software co-design, logic and behavioral synthesis, logic synthesis and technology mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction), buffer insertion, CAD for datapath synthesis, algorithms and complexity analysis. 4. Low Power and Power Aware Design: circuits, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools. 5. Testing, Reliability, Fault-Tolerance: digital/analog/mixed-signal testing, design for testability and reliability, test vector compression, silicon debug and diagnosis, online testing techniques, static and dynamic defect- and fault-recoverability, and variation-aware design. 6. Emerging Technologies: 3D integration, probabilistic architectures, optical interconnects, microfluidics, CNT, SET, RTD, QCA, VLSI aspects of sensor and sensor network, and CAD tools for emerging technology devices and circuits. 7. Post-CMOS VLSI: evolutionary computing, optical computing, quantum computing, reversible logic, spin-based computing, biological computation, nanotechnology, molecular electronics, quantum devices, biologically-inspired computing. Emphasis should be on the analysis, novel circuits and architectures, modeling, CAD tools, and design methodologies. IMPORTANT DATES * Paper submission deadline : November 30th, 2008 * Special session proposal deadline : December 20th, 2008 * Acceptance notification : February 5th, 2009 * Camera-ready paper due : March 3rd, 2009 SUBMISSION INSTRUCTIONS Authors are invited to submit full-length (6 pages maximum), original, unpublished papers along with an abstract of at most 200 words. To enable blind review, the author list should be omitted from the main document. Previously published papers or papers currently under review for other conferences/journals should not be submitted and will not be considered. Electronic submission in PDF format to the http://www.glsvlsi.org website is required. Author and contact information (name, street/mailing address, telephone, fax, e-mail) must be entered during the submission process. * Paper Format: Submissions should be in camera-ready two-column format, following the ACM proceedings specifications located at: http://www.acm.org/sigs/pubs/proceed/template.html and the classification system detailed at: http://www.acm.org/class/1998/ * Paper Publication and Presenter Registration: Papers will be accepted for regular or poster presentation at the symposium. Every accepted paper MUST have at least one author registered to the symposium by the time the camera-ready paper is submitted; the author is also expected to attend the symposium and present the paper. SPONSORS GLSVLSI 2009 is kindly supported and sponsored by the following companies and institutions: + ACM SIGDA + IEEE Council on Electronic Design Automation (CEDA) + IEEE Circuits and Systems Society (CASS) ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. 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