=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membership. Circulation: 2,700 =============================================================================== 1 September 2008 ACM/SIGDA E-NEWSLETTER Vol. 38, No. 17 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Soheil Ghiasi Contributing author: Matthew Guthaus Contributing author: Umit Y Ogras Contributing author: Marc Riedel Contributing author: Lin Yuan (2) What is a configurable, extensible processor? Contributing author: Grant Martin, Chief Scientist, Tensilica From: Deming Chen (3) Paper Submission Deadlines From: Debjit Sinha (4) Upcoming Conferences and Symposia From: Debjit Sinha (5) Upcoming Funding Opportunities From: Qinru Qiu (6) GLSVLSI 2009 Call for Papers From: David Atienza Alonso (7) Call For Nominations : 2008 ACM Outstanding Ph.D. Dissertation Award in EDA - Updated Nomination Requirements From: Radu Marculescu (8) Call For Participation : Seventh CADathlon at ICCAD From: Jennifer Dworak =============================================================================== Dear ACM/SIGDA members, In this issue, we have reprinted the "What Is ..." column from Grant Martin, the Chief Scientist of Tensilica. Our target is to publish a new and original "What is ..." column every month. We welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Qing Wu, E-Newsletter Editor; Matthew Guthaus, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Debjit Sinha, E-Newsletter Associate Editor; Lin Yuan, E-Newsletter Associate Editor; Soheil Ghiasi, E-Newsletter Associate Editor; Deming Chen, E-Newsletter Associate Editor; Umit Ogras, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "Startup Introduces 'Unclonable' Chip Technology" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210500113 A Palo Alto security and authentication startup known for its "unclonable" silicon chips, relaunched Wednesday as Verayo in an effort to move its focus from government defense contracts to commercial markets. "Virtual Mixer Harnesses DSP" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210500338 Studio-quality audio processing no longer requires expensive gear, according to Universal Audio Inc. (Scotts Valley, Calif.), which has harnessed up to four Analog Devices' Sharc (Super Harvard ARchitecture Computer) digital-signal processors on a single PCI Express board. "Researchers Grow Nano-Scale Wire Nets" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210300412 Researchers at Boston College say they have produced a flexible webbing of nano-scale wires that may eventually be used in electronics and energy harvesting. "Reading The Tea Leaves: How Deep Will EDA Losses Go?" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210201508 The four largest EDA companies have now all reported their financial results for their respective quarters. Only Synopsys had a positive result, while Cadence, Magma, and Mentor all reported losses. The obvious questions are: what are the causes, how deep will the losses go, and how long will the downturn last. Forecasting is usually a tricky business, but in this case, some properties of the near future behavior of the EDA industry are clearly visible. All that is required is a dispassionate reading of what the CEO of these companies are saying. "Researchers Create Quantum Repeater" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210201474 Scientists from Austria, China and Germany have implemented a stable quantum repeater. The device has the potential to obtain a central function in future quantum effect-based communication networks. "China Readies First Multicore Godson CPUs" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210201017 Chinese researchers are preparing the first multicore versions of Godson, the country's first homegrown microprocessor, with four- and eight-core designs scheduled to tape out in the coming months. China hopes to build a petaflops high-performance computer based on the Godson-3 in 2010. "IBM Demonstrates Light-Emitting Nanotube" http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210200443 Electric control of the spectrum, direction and efficiency of light-emitting nanotubes (LENs) has been demonstrated by researchers at IBM Corp.'s Thomas J. Watson Research Center, bringing silicon photonics one step closer to reality. "On-Chip Test Capabilities Solve The Analog-Test Problem For High-Speed Serial Interfaces" http://www.edn.com/article/CA6586230.html A small amount of on-chip analog-test hardware offers big payoffs when you are dealing with high-speed serial interfaces. As part of the serial-interface IP (intellectual property) or of an IP wrapper, the test hardware can provide views of the interface's performance that are more accurate than those of expensive external test equipment. As high-speed serial interfaces increase in speed, on-chip diagnostics will be the only way to verify that serial links - particularly the PHY (physical) interface - are working correctly at the designated speed. "Heard At Hot Chips: The Hype Grows Around Photovoltaic Power Generation" http://www.edn.com/blog/1690000169/post/90032409.html In an uncharacteristically non-integrated-circuit keynote topic, the Hot Chips conference this week offered up Dick Swanson, co-founder, president and chief technical officer of SunPower, to give a brief history of the company. Along the way Swanson outlined the technical evolution that brought the company from, more or less literally, the middle of the desert to a rooftop near you, and may well take it back again. And he gave some examples of the kind of numbers-bending hype that is gradually raising suspicions about the entire sector. "Electronic-System-Level Design: Is There Fire Beneath The Smoke?" http://www.edn.com/article/CA6586221.html It was a shimmering promise on the horizon: As SOCs (systems on chips) became more complex, we would simply move from RTL (register-transfer level) to the next-higher level of abstraction - what some experts called ESL (electronic-system-level) design. We would express the behavior of the system in a high-level language, such as C++. We would model and explore the system at that level, partition it into hardware and software components, and then push a button. Scripts and ESL-synthesis tools would digest our ESL design and give us back a nearly optimal RTL design or even a netlist together with the necessary software. Design productivity would once again be ahead of complexity. "FPGA IP Completes Wireless-Backhaul Method" http://www.edn.com/article/CA6586233.html Wintegra's third-generation UFE3 (universal-front-end-3) IP (intellectual-property) core for high-channel-density, wireless-backhaul designs provides an upgrade path for designers migrating voice-centric cellular systems to high-capacity data-plus-voice-capable designs. The core works with the company's WinPath2 processor and PMC-Sierra's Temux family of framers and mappers. The IP core plus Wintegra's WinPath2 processors at the central office provide bidirectional conversion of 8064 legacy DS0 channels to GbE (gigabit Ethernet), with carrier Ethernet as the link to remote cell sites. The core enables a fully channelized application running any protocol from a list that includes PWE3 (pseudowire end-to-end emulation), MC/ML-PPP (multiclass/multilink point-to-point protocol), IMA (inverse multiplexing over asynchronous transfer mode), and MFR (multilink-frame relay). ============================================================================== What Is A Configurable, Extensible Processor? ---------------------------- Grant Martin, Chief Scientist, Tensilica We're all familiar with fixed Instruction Set Architecture (ISA) processors, such as Intel or AMD x86-class processors, and in the embedded design area, ARM cores, for example. As well as these general purpose cores, there are also fixed ISA processors that are more specific to a particular problem domain, such as Digital Signal Processors (DSPs). But the product requirements of many embedded applications, especially for power-sensitive and low energy mobile media devices and cellphones, open up an opportunity to use Application-Specific Instruction set Processors (ASIPs) with highly application-oriented structural parameters and specialized instructions suitable for optimizing a particular application. Audio and video applications are good examples of product areas where the use of a customized ASIP for specific tasks may reduce energy consumption by a factor of 3 to 10 or more, thus allowing portable devices to operate for greatly increased periods between battery charges. Even the field of high performance computing may make use of ASIPs as the reduction in energy consumption and gain in performance for specific high-end tasks, such as climate modelling, may make the use of thousands or even millions of ASIPs very appropriate. The design of appropriate ASIPs for particular applications follows one of two basic strategies. The first is similar to what is done with fixed ISA processors: the ASIP is designed by hand, including all structural hardware parameters and specialized instructions. Once the ISA is decided on, and the hardware design reaches a certain stage, the software tool chain, which normally comprises assemblers, linkers, compilers, instruction set simulators, and many other associated parts of the development suite, is created. This may also be done by hand. In particular, developing appropriate compiler optimizations to make use of specialized instructions may be difficult and users of ASIPs may need to manually invoke them in their target code using macros or pragmas. The other major strategy for ASIP design is to use an automated tool flow to generate hardware and the software tool chain. These types of flows may be based on generating a completely new micro-architecture from scratch for each new ASIP, or by configuring and extending a base RISC ISA with a set of structural parameters drawn from a configuration space, and with a set of instruction extensions based on an extension space. The latter is what is generally known as a configurable, extensible processor. Over the past decade, several commercial offerings and several academic research projects have explored the concept of configurable, extensible processors. Commercial offerings include Tensilica and ARC; research projects include AsipMeister, NISC, LISA, and several others. In many cases, most or a large portion of the ISA, especially the specialized instruction additions, are described in an Architectural Description Language (ADL), also known in this context as a Processor Description Language. Strategies for generating the hardware and software tool chain include compilation of the ADL, via special tools that will automatically create the HW (RTL) and SW (intermediate instruction format) representations. An alternative mechanism for simpler instructions may be by using templatized RTL generators for HW implementation. SW infrastructure tools such as assemblers, compilers, disassemblers and debuggers may be totally generated from scratch for each different ASIP instance, thus leading to unique tools for each ASIP. However, an alternative that is especially relevant for extensible processors is to have a SW tool chain with defined extension mechanisms that can link in dynamically (at runtime) compiled libraries that reflect the syntax and semantics of the set of instruction extensions, produced by the ADL compiler. In addition, coarse-grained structural parameters - for example, for register file size or interface widths - may be used in generating a new tool chain from scratch, or instead be dynamically read in from parameter files at runtime and thus constrain the operations of the SW tools to the defined configuration of the ASIP. As an example of the kinds of options that configurable, extensible ASIPs provide, configuration possibilities may include the number and kinds of local and system memory interfaces, the inclusion or exclusion of certain ALU units such as floating point units, multipliers and multiply-accumulators, bit width customizations, sizes of register files, diagnostic and tracing capabilities, use of VLIW style multi-operation instructions, interrupts and exceptions, direct FIFO interfaces, multiple load-store, and pipeline sizing. In addition to these rather coarse-grained structural configuration options, use of ADLs to define specialization or extension instructions tuned to specific application and code requirements may have an wide range - from none or just a few new instructions, to many hundreds of complex multi-cycle instructions designed to speed up computations for particular algorithms while minimizing power consumption through precise tuning of instruction characteristics to the specific source code. The use of ASIPs in all kinds of products, applications and research is growing and there are many resources available for those interested at exploring this area further. The references are just a starting point. To Explore further, please look at: Paolo Ienne and Rainer Leupers (editors), Customizable Embedded Processors: Design Technologies and Applications, Elsevier, 2007. http://www.elsevierdirect.com/product.jsp?isbn=9780123695260 Prabhat Mishra and Nikil Dutt (editors), Processor Description Languages, Elsevier, 2008. http://www.elsevierdirect.com/product.jsp?isbn=9780123742872 Chris Rowen and Steve Leibson, Engineering the Complex SOC: Fast, Flexible Design with Configurable Processors, Prentice-Hall PTR, 2004. http://www.tensilica.com/news_events/book.htm Steve Leibson, Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores, Elsevier, 2006. http://www.elsevierdirect.com/product.jsp?isbn=9780123724984 R. E. Gonzalez, Xtensa: a configurable and extensible processor, IEEE Micro, March/April 2000, pp. 60-70. Steve Leibson and James Kim, Configurable processors: a new era in chip design, IEEE Computer, July, 2005, pp. 51-59. Michael Wehner, Leonid Oliker and John Shalf, Towards Ultra-High Resolution Models of Climate and Weather, International Journal of High Performance Computing Applications, May 2008, pp. 149-165. http://portal.acm.org/citation.cfm?id=1361718.1361723 ============================================================================== Paper Submission Deadlines: ---------------------------- IP'08 . IP-Based System Design Grenoble, France Dec 3-4, 2008 Deadline: Sep 21, 2008 http://www.design-reuse.com/ip08/ ISSCC'09 - Int'l Solid-State Circuits Conference San Francisco, CA Feb 8-12, 2009 Deadline: Sep 22, 2008 http://isscc.org/isscc/ ISPD'09 - Int'l Symposium on Physical Design (sponsored by SIGDA) San Diego, CA Mar 29 - Apr 1, 2009 Deadline: Oct 5, 2008 http://www.ispd.cc/ ISCAS'09 - Int'l Symposium on Circuits and Systems Taipei, Taiwan May 24-27, 2009 Deadline: Oct 10, 2008 http://iscas2009.org/ ISQED'09 - Int'l Symposium on Quality Electronic San Jose, CA Mar 16-18, 2008 Deadline: Oct 10, 2008 http://www.isqed.org/ SPL'09 - Southern Conference on Programmable Logic SãCarlos, Brazil Apr 1-3, 2009 Deadline: Nov 17, 2008 http://www.splconf.org/ GLSVLSI '09 - Great Lakes Symposium on VLSI Boston, Massachusetts May 10-12, 2009 Deadline: November 30th, 2008 http://www.glsvlsi.org/ DAC'09 - Design Automation Conference (sponsored by SIGDA) San Francisco, CA Jul 26-31, 2009 Deadline: Dec 19, 2008 http://www.dac.com/ ============================================================================== Upcoming Symposia, Conferences and Workshops: --------------------------------------------- SBCCI'08 - Symposium on Integrated and Systems Design (sponsored by SIGDA) Gramado, Brazil Sep 1-4, 2008 http://www.inf.ufrgs.br/chipinthepampa2008/sbcci.php DSD'08 - Euromicro Conference on Digital System Design Parma, Italy Sep 3-5, 2008 http://dsd08.iet.unipi.it/index.htm FPL'08 - Int'l Conference on Field-Programmable Logic and Applications Heidelberg, Germany Sep 8-10, 2008 http://www.kip.uni-heidelberg.de/fpl08/cms/website.php PATMOS'08 - Power and Timing Modeling, Optimization & Simulation Lisbon, Portugal Sep 10-12, 2008 http://algos.inesc-id.pt/patmos/home.shtml?general CICC'08 - Custom Integrated Circuits Conference San Jose, CA Sep 21-24, 2008 http://www.ieee-cicc.org/ VLSI-SoC'08 - Int'l Conference on Very Large Scale Integration Rhodes Island, Greece Oct 13-15, 2008 http://vlsi.ee.duth.gr/vlsisoc-2008/ CODES+ISSS'08 - Int'l Conference on Hardware-Software Codesign and System Synthesis (sponsored by SIGDA) Atlanta, GA Oct 19-24, 2008 http://www.codes-isss.org/ PACT'08 - Int'l Conference on Parallel Architectures and Compilation Techniques Toronto, Canada Oct 25-29, 2008 http://www.eecg.toronto.edu/pact/ ICCAD'08 - Int'l Conference on Computer-Aided Design (sponsored by SIGDA) San Jose, CA Nov 10-13, 2008 http://www.iccad.com/ MICRO'08 - Int'l Symposium on Microarchitecture Lake Como, Italy Nov 8-12, 2008 http://www.microarch.org/micro41/ ICPADS'08 - Int'l Conference on Parallel and Distributed Systems Melbourne, Australia Dec 8-10, 2008 http://www.deakin.edu.au/conferences/icpads2008/ EUC'08 - Int'l Conference on Embedded and Ubiquitous Computing Shanghai, China Dec 17-20, 2008 http://epcc.sjtu.edu.cn/euc2008/ HiPC'08 - Int'l Conference on High Performance Computing Bangalore, India Dec 17-20, 2008 http://www.hipc.org/ HiPEAC'09: Int'l Conference on High Performance Embedded Architectures & Compilers Paphos, Cyprus Jan 25-28, 2009 http://www.hipeac.net/conference ============================================================================== Upcoming Funding Opportunities ---------------------------------- DARPA Strategic Technologies (BAA 08-10) Deadline: February, 2009 http://www.darpa.mil/sto/solicitations/BAA08-10/index.html DOE Advanced Scientific Computing Research (ASCR) (DE-PS02-08ER08-01) Deadline: September 30, 2008 http://www.science.doe.gov/grants/FAPN08-01.html DOD Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html SPINS in Semiconductors Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Artificial Intelligence Technologies Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Quantum Information Science and Technology Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Microsystems Technology Office-Wide Deadline: January 14, 2009 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html Modeling and Simulation for Information Systems Research Deadline: FY 10 should be submitted by June 1, 2009 http://fedbizopps.cos.com/cgi-bin/getRec?id=20061030a9 Test and Evaluation Deadline: July 2009 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Cognition and Neuroergonomics Collaborative Technology Alliance (CTA) - W911NF-08-R-0014 Deadline: July 01, 2009 http://fedbizopps.cos.com/cgi-bin/getRec?id=20080811a12 Cognitive Neuroscience (CNS) or Other Emerging or Leap-Ahead Technologies That Offer to Dramatically Advance Submarine Sonar or Other Advanced Underwater Systems Deadline: July 2009 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Information Warfare: Offensive and Defensive Counterinformation - BAA-06-12-IFKA Deadline: Continuous until December 2009 https://www.fbo.gov/index?s=opportunity&mode=form&id=5a4214baae590a1808f3077a0e7b9244&tab=core&_cview=1 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.rdecom.army.mil/STTC/2006_N61339-05-R-0095__BAA_FY06_Amendment_0001.pdf Army Research Office (ARO) Broad Agency Announcement for Basic and Applied Scientific Research (W911NF-07-R-0003) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 ARL/ARO Core Broad Agency Announcement for Basic and Applied Scientific Research for Fiscal Years 2007 through 2011 (W911NF-07-R-0001) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 Systems and Software (AFOSR-BAA-2008-1) Deadline: Continuous http://www.wpafb.af.mil/shared/media/document/AFD-080212-048.pdf NSF CreativeIT - NSF 08-572 Deadline: September 26, 2008 http://www.nsf.gov/pubs/2008/nsf08572/nsf08572.htm Engineering Design and Innovation (EDI) Deadline: October 1, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13340 Multicore Chip Design and Architecture: (MCDA) - NSF 08-584 Deadline: October 17, 2008 http://www.nsf.gov/pubs/2008/nsf08584/nsf08584.htm Collaborative Research in Computational Neuroscience (CRCNS) Deadline: February 26, 2008 October 30, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=5147&org=CISE&from=home Accelerating Discovery in Science and Engineering Through Petascale Simulations and Analysis (PetaApps) - NSF 08-592 Deadline: October 30, 2008 http://www.nsf.gov/pubs/2008/nsf08592/nsf08592.htm TeraGrid Phase III: eXtreme Digital Resources for Science and Engineering (XD) Deadline: November 04, 2008 http://www.nsf.gov/pubs/2008/nsf08571/nsf08571.htm High Performance Computing Acquisition: Towards a Petascale Computing Environment for Science and Engineering - NSF 05-625 Deadline: November 28, 2008 http://www.nsf.gov/pubs/2005/nsf05625/nsf05625.htm Information and Intelligent Systems (IIS): Core Programs Deadline: Medium Projects October 1, 2008 - October 31, 2008 Large Projects November 1, 2008 - November 28, 2008 Small Projects December 1, 2008 - December 17, 2008 http://www.nsf.gov/div/index.jsp?div=IIS Computing and Communication Foundations (CCF): Core Programs Deadline: Medium Projects October 1, 2008 - October 31, 2008 Large Projects November 1, 2008 - November 28, 2008 Small Projects December 1, 2008 - December 17, 2008 http://www.nsf.gov/pubs/2008/nsf08577/nsf08577.htm#pgm_desc_txt USDA Electronics/Computer Engineer - RA-08-065H (postdoctoral opportunity) Deadline: Continuous http://www.afm.ars.usda.gov/divisions/hrd/hrdhomepage/vacancy/08065.htm Microsoft Microsoft Research and Live Labs Ph.D. Fellowship Deadline: October 17, 2008 http://research.microsoft.com/aboutmsr/jobs/fellowships/apply_us.aspx DOE Lawrence Fellowship Deadline: November 03, 2008 https://fellowship.llnl.gov/ Sigma Delta Epsilon/Graduate Women in Science, Inc. Sigma Delta Epsilon (SDE) Fellowships Deadline: January 15, 2009 http://www.gwis.org/grants/default.htm ============================================================================== GLSVLSI 2009 Call for Papers ------------------------------- IEEE/ACM GSLVSLI 2009 19th Great Lakes Symposium on VLSI Systems May 10-12, 2008, Boston, Massachusetts, USA http://www.glsvlsi.org/ ABOUT GLSVLSI: The 19th edition of GLSVLSI will be held in Boston, Massachusetts. Original, unpublished papers, describing research in the general area of VLSI are solicited. Both theoretical and experimental research results are welcome. Proceedings will be published by the ACM and will be available through the ACM Digital Library and IEEE Xplore. For detailed information, visit http://glsvlsi.org/. PROGRAM TRACKS: 1. VLSI Design: design of ASICs, microprocessors/micro-architectures, embedded processors, analog/digital/mixed-signal systems, NoC, interconnects, memories, and FPGAs. 2. VLSI Circuits: analog/digital/mixed-signal circuits, RF and communication circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits, arithmetic circuits. 3. Computer-Aided Design (CAD): hardware/software co-design, logic and behavioral synthesis, logic synthesis and technology mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction), buffer insertion, CAD for datapath synthesis, algorithms and complexity analysis. 4. Low Power and Power Aware Design: circuits, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools. 5. Testing, Reliability, Fault-Tolerance: digital/analog/mixed-signal testing, design for testability and reliability, test vector compression, silicon debug and diagnosis, online testing techniques, static and dynamic defect- and fault-recoverability, and variation-aware design. 6. Emerging Technologies: 3D integration, probabilistic architectures, optical interconnects, microfluidics, CNT, SET, RTD, QCA, VLSI aspects of sensor and sensor network, and CAD tools for emerging technology devices and circuits. 7. Post-CMOS VLSI: evolutionary computing, optical computing, quantum computing, reversible logic, spin-based computing, biological computation, nanotechnology, molecular electronics, quantum devices, biologically-inspired computing. Emphasis should be on the analysis, novel circuits and architectures, modeling, CAD tools, and design methodologies. IMPORTANT DATES * Paper submission deadline : November 30th, 2008 * Special session proposal deadline : December 20th, 2008 * Acceptance notification : February 5th, 2009 * Camera-ready paper due : March 3rd, 2009 SUBMISSION INSTRUCTIONS Authors are invited to submit full-length (6 pages maximum), original, unpublished papers along with an abstract of at most 200 words. To enable blind review, the author list should be omitted from the main document. Previously published papers or papers currently under review for other conferences/journals should not be submitted and will not be considered. Electronic submission in PDF format to the http://www.glsvlsi.org website is required. Author and contact information (name, street/mailing address, telephone, fax, e-mail) must be entered during the submission process. * Paper Format: Submissions should be in camera-ready two-column format, following the ACM proceedings specifications located at: http://www.acm.org/sigs/pubs/proceed/template.html and the classification system detailed at: http://www.acm.org/class/1998/ * Paper Publication and Presenter Registration: Papers will be accepted for regular or poster presentation at the symposium. Every accepted paper MUST have at least one author registered to the symposium by the time the camera-ready paper is submitted; the author is also expected to attend the symposium and present the paper. SPONSORS GLSVLSI 2009 is kindly supported and sponsored by the following companies and institutions: + ACM SIGDA + IEEE Council on Electronic Design Automation (CEDA) + IEEE Circuits and Systems Society (CASS) ============================================================================== Call For Nominations ---------------------- 2008 ACM Outstanding Ph.D. Dissertation Award in EDA http://www.sigda.org/opda.html Submission Deadline: September 15, 2008 Award Description: Design automation has gained widespread acceptance by the VLSI circuits and system design community. Advancements in computer-aided design (CAD) methodologies, algorithms, and tools have become increasingly important to cope with the rapidly growing design complexity, higher performance and low-power requirements, and shorter time-to-market demands. To encourage innovative, ground-breaking research in the area of electronic design automation, the ACM's Special Interest Group on Design Automation (SIGDA) has established an ACM award to be given each year to an outstanding Ph.D. dissertation that makes the most substantial contribution to the theory and/or application in the field of electronic design automation. The award consists of a certificate and a check for $1,000 and is presented at the Design Automation Conference, which is held in June/July of each year. The award is selected by a committee of experts from academia and industry in the field and appointed by ACM in consultation with the SIGDA Chair. Nomination requirements and procedure: * Each department of any university may nominate at most TWO Ph.D. dissertations with final submission date between July 1st of the previous year and June 30th of the current year. * Each nomination package must be emailed by September 15 and should consist of: 1. The PDF file of the Ph.D. dissertation. 2. A statement (up to two pages) from the nominee explaining the significance and major contributions of the work. 3. A nomination letter from nominee's department chair or dean of the school endorsing the application. 4. Optionally, up to three additional letters of recommendation from experts in the field. These letters may be included in the package or sent separately to the address below. The nomination materials should be emailed at: opda@acm.org (Subject: ACM Outstanding Ph.D. Dissertation Award in EDA). ============================================================================== Call For Participation ---------------------- Seventh CADathlon at ICCAD, November 9, 2008 For the seventh year in a row, ACM/SIGDA organizes the EDA programming contest at ICCAD on Sunday, November 9, 2008 The CADathlon is a challenging, all-day, programming competition focusing on practical problems taken from the field of Computer Aided Design and Electronic Design Automation in particular. The contestants are tested on their CAD knowledge, problem solving, programming, and teamwork skills. The contest provides academia and industry a unique opportunity to focus attention on the best and brightest of the next generation of CAD professionals. The CADathlon is also intended to assist in attracting top students to the EDA field. The contest is open to 2-person teams of graduate students specializing in CAD currently full-time enrolled in a Ph.D. granting institution in any country. Students will be selected based on their academic and course backgrounds and their relevant EDA programming experiences. Some travel grants will be provided for qualifying students. The CADathlon competition consists of six problems in the following areas: circuit analysis, physical design, logic and behavioral synthesis, system design and analysis, functional verification, and timing, test, and manufacturing. Solutions will be judged on correctness and efficiency. Where appropriate, partial credit might be given. The team that earns the highest score is declared the winner. In addition to handsome trophies, the first place team's prize is a $2,000 cash award. The second place team's prize is a $1,000 cash award. The CADathlon competition is sponsored by ACM/SIGDA and several companies from the EDA industry. These sponsors are instrumental in helping us provide travel grants to many teams, and in providing the handsome prize money. We are usually able to offer all participants some funding in the form of free lodging and a selected number are found eligible for a travel grant. Our policy is to assist the needy and ensure international representation. The application deadline is September 29, 2008 For the registration application, detailed contest information and sample problems from last year's competition, please visit the ACM/SIGDA web site: http://www.sigda.org/programs/cadathlon For additional questions, please contact members of the CADathlon organizing committee: Prof. Jennifer Dworak, Jennifer_Dworak@brown.edu, Donald Chai, donald.chai@gmail.com, or Satrajit Chatterjee, satrajit.chatterjee@intel.com, or SIGDA representative: Prof. Matthew Guthaus, mrg@soe.ucsc.edu Jennifer Dworak CADathlon Program Chair ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. 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