=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membership. Circulation: 2,700 =============================================================================== 15 July 2008 ACM/SIGDA E-NEWSLETTER Vol. 38, No. 14 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Soheil Ghiasi Contributing author: Matthew Guthaus Contributing author: Umit Y Ogras Contributing author: Marc Riedel Contributing author: Lin Yuan (2) DAC Best Paper Awards From: Igor Markov (3) What is the design challenge for on-chip speed-of-light communication? Authors: C.K. Cheng and James Buckwalter Univ. of California at San Diego From: Deming Chen (4) Paper Submission Deadlines From: Debjit Sinha (5) Upcoming Conferences and Symposia From: Debjit Sinha (6) Upcoming Funding Opportunities From: Qinru Qiu (7) Call For Nominations : 2008 ACM Outstanding Ph.D. Dissertation Award in EDA - Updated Nomination Requirements From: Radu Marculescu =============================================================================== Dear ACM/SIGDA members, In this issue, we include a new topic "What is the design challenge for on-chip speed-of-light communication?" contributed by Prof. C.K. Cheng and Prof. James Buckwalter of Univ. of California at San Diego. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Qing Wu, E-Newsletter Editor; Matthew Guthaus, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Debjit Sinha, E-Newsletter Associate Editor; Lin Yuan, E-Newsletter Associate Editor; Soheil Ghiasi, E-Newsletter Associate Editor; Deming Chen, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "Project Galaxy to Spend $6 Million Researching GALS" http://www.eetimes.com/rss/showArticle.jhtml?articleID=209400414&cid=RSSfeed_eetimes_newsRSS A 4 million euro (about $6.4 million) European collaborative research project called Project Galaxy has begun to develop a design process for globally asynchronous, locally synchronous (GALS) architecture chips together with novel network-on-chip (NoC) capabilities. "Semiconductor Device Failure Analysis Improved" http://www.electronicstalk.com/news/mai/mai111.html Enhanced products offer major improvements in how net failures can be correlated to inline defect data and failed net frequency. Magma Design Automation has improved its Knights LogicMap and IntensityMap software that enable faster, more accurate semiconductor device failure analysis and debug for logic devices The enhanced products offer major improvements in how net failures can be correlated to inline defect data (random defects) and failed net frequency (systematic defects) "Semiconductor Equipment Sales to Fall 20% in 2008, SEMI Reports" http://www.edn.com/article/CA6578733.html While this drop follows 6% market growth in 2007, SEMI believes the semiconductor manufacturing equipment industry will experience a rebound with annual growth of 13% in 2009, and 6% in 2010. Semiconductor Equipment and Materials International (SEMI) President and CEO Stanley T Myers today reported at the Semicon West trade show here that the industry association expects 2008 semiconductor manufacturing equipment sales will fall approximately 20% this year to $34.12 billion. "Tips On How To Build A Better Home For Biological Parts' http://www.sciencedaily.com/releases/2008/07/080716120648.htm Researchers at the Virginia Bioinformatics Institute (VBI) at Virginia Tech have compiled a series of guidelines that should help researchers in their efforts to design, develop and manage next-generation databases of biological parts. The stakes are high: the concept of biological parts is essential if methods developed in other fields of engineering are to be applied to biology. If successful, this approach will result in significant productivity gains for the biotechnology industry. "Synthetic Biology Aims to Solve Energy Conundrum" http://www.guardian.co.uk/science/2008/jun/19/chemistry.agriculture Designer enzymes are big business as the need to produce viable biofuels grows - but can they offer a long-term alternative? You can power laptops - and, potentially cars - using hydrogen extracted from water. The trouble is that it takes a lot of electricity. A simpler way would be to do it naturally, using enzymes - proteins which catalyse reactions - and bacteria. These do exist: certain green algae and "cyanobacteria" can split water using photosynthesis to produce molecular hydrogen. "Novellus Execs Lay Out Case For Industry, Market Growth Opportunities" http://www.solid-state.com/display_article/334313/5/none/none/TCHNE/Novellus-execs-lay-out-case-for-industry,-market-growth-opportunitie There's a certain amount of schizophrenia around SEMICON West this year. On one hand, the photovoltaic sector is growing like kudzu. Growth exceeds 50%, money is pouring into the sector, and solar is one of the few industries that actually benefits from high energy prices. The future looks very bright indeed. "Asyst Introduces VAO Software Platform to Manage Fab Data; Toshiba Semi is First User" http://www.solid-state.com/display_news/164685/5/HOME/Asyst_introduces_VAO_software_platform_to_mnage_fab_data; Asyst Technologies, Inc., the leader in Agile Automation(TM), today announced the commercial availability of its VAO(TM) (Visualize Analyze Optimize) Productivity Solution. VAO coordinates data acquisition from, and provides control of, a wide range of factory systems, including Automated Material Handling Systems (AMHS) and process and metrology tools, with the resulting information available in real-time. "Pushing Pixels" http://www.technologyreview.com/Infotech/21088/?a=f Kodak's latest sensor enables digital cameras to enter the 50-megapixel range. Last week, Kodak launched the first ever 50-megapixel camera sensor. While such high resolution goes beyond the needs of most consumers, for professional photographers the new sensor will enable photographs to be taken at an unprecedented level of detail. "UMC Chairman, CEO Jackson Hu Resigns" http://www.edn.com/article/CA6579103.html UMC today announced that Jackson Hu has resigned as chairman and CEO of the company and will pursue a role as a senior advisor to the foundry. UMC immediately filled the seats, reporting that Stan Hung (pictured, left)has been elected as chairman and Shih-Wei Sun will take over the position of CEO as of a board meeting in Taiwan earlier today. The board meeting election was held after Hu announced his decision to resign from active leadership of the company. The company said the appointment of a .youthful, professional management team. is aimed at the .revitalization of UMC. and the .enhancement. of its technology focus. "Ramtron Manufacturing Defect to Result in Charge" http://www.edn.com/article/CA6578812.html Ramtron says a manufacturing process defect in its memory device combined with a unique use within its customer.s end product resulted in device failures. Ramtron International Corp has become the second company this month to announce a product failure and could face a financial charge because of it. The fabless developer and supplier of nonvolatile FRAM (ferroelectric random access memory) and integrated semiconductor products announced on Monday that one of its customers has requested payment for losses resulting from in-field failures of one of its memory products. Ramtron did not identify the customer or state which of its memory products was involved in the failures. "IMEC, Qualcomm to Research 3D Integration" http://www.edn.com/article/CA6578240.html?industryid=47037 The 3D technical research program focuses on 3D wafer-level packaging and 3D stacked ICs to find applications for the cost-effective use of 3D interconnects at different levels of the wiring hierarchy in a chip, and aims to include the development and demonstration of the IP and tools necessary for designing in three dimensions. "Intel Invests in DNA Sequencing Company" http://www.edn.com/article/CA6578302.html?industryid=47037 Pacific Bioscience's single-molecule, real-time DNA sequencing platform is expected to allow for the first time the observation of natural DNA synthesis by a DNA polymerase as it occurs. Intel Corp has co-led a $100 million investment round that is expected to push commercial development of a start-up.s DNA sequencing platform. The single-molecule, real-time (SMRT) DNA sequencing platform from four-year-old Pacific Bioscience is expected to allow for the first time the observation of natural DNA synthesis by a DNA polymerase as it occurs. "Semiconductor R&D Spending Growth to Show 8% Rise in 2008, IC Insights Forecasts" http://www.edn.com/article/CA6577202.html?industryid=47037 As next-generation IC processes have become more expensive to develop and IC design costs are exploding, R&D and engineering budgets have increased at a faster rate than the industry.s sales growth since the early 1990s. As such, R&D and engineering expenditures increased at a compound average growth rate of 12.7% between 1990 and 2007, while semiconductor sales grew at a CAGR of 9.9% in the 17-year period. "Cadence Expands System-Level Offerings With Introduction of C-to-Silicon Compiler" http://money.cnn.com/news/newsfeeds/articles/marketwire/0414135.htm Cadence Design Systems, Inc., the leader in global electronic design innovation, today introduced Cadence® C-to-Silicon Compiler, a high-level synthesis product that improves designer productivity up to 10 times in creating and re-using system-on-chip IP. The innovative technology in C-to-Silicon Compiler helps bridge the gap between register transfer level (RTL) models -- commonly used to verify, implement, and integrate SoCs -- and system-level models, usually written in C/C++ and SystemC. ============================================================================== DAC Best Paper Awards ---------------------------- This year's Best Paper awards, selected from 147 regular technical papers presented at this year's DAC, were given to authors from Texas A&M and Stanford University. Each award carries a $1,500 prize. Award winners are Wei Dong, Peng Li and Xiaoji Ye of Texas A&M University and Sung-Boem Park and Subhasish Mitra of Stanford University. Dong, Li and Ye authored, "WavePipe: Parallel Transient Simulation of Analog and Digital Circuits on Multi-core Shared-memory Machines," a novel approach for parallel transient simulation, a process that can significantly speed up computer-aided design (CAD) tools. Authors Park and Mitra presented, "IFRA: Instruction Footprint Recording and Analysis for Post-silicon Bug Localization in Processors," a new debugging method for application-specific instruction-set processors, allowing information to be scanned at a high speed. Ten papers were nominated by the technical subcommittees for consideration for Best Paper from the 147 technical conference papers. A special best paper selection committee comprised of five distinguished individuals in the EDA community across faculty, industry and various geographies reviewed the nominated papers. They visited all best paper presentations at the conference, and in a closed meeting Wednesday afternoon of DAC selected the two best overall papers. Best Paper awards were announced June 12 before DAC's Thursday keynote. "Both of these papers highlight topics of high importance in the EDA industry," remarks Patrick Groeneveld, the 45th DAC technical program committee co-chair and Magma's chief technologist. "They are an example of the problem-solving ability occurring at the highest levels of industry and academia. We are proud of DAC's continuing role as a focal point for the latest research and development in our industry. It remains the most relevant event in the EDA industry and is the place where electronic design meets." ============================================================================== What is the Design Challenge For On-Chip Speed-of-Light Communication? ---------------------------------------------------------------------- Authors: C.K. Cheng and James Buckwalter Univ. of California at San Diego As technology scales, on-chip interconnects become one of the most critical factors in determining the system performance and power consumption [1-3]. Since the wire resistance per unit length is inversely proportional to its cross section, the wire incurs high-signal attenuation as its cross section shrinks. Current practice views the wires as RC segments. Buffers are inserted between RC segments to boost a faster full voltage swing [4,5]. The inserted buffers regenerate the voltage level from buffer inputs instead of relaying the signals as waves. The full swing of RC segments requires high latency and consumes power. On-chip transmission lines offer the potential to break the wall that blocks the interconnect performance [6-11]. First, the transmission line can allow the signal to travel at the speed of light in the medium. Second, the signal toggles as wave instead of enforced electronic charges and thus saves power. In order to make the on-chip transmission line competitive in practice, we face the following challenges. 1. The signal attenuation: The bound of signal attenuation determines the dimensions of the wires. The received signal should be kept large enough to be immune from crosstalk and noise. The attenuation is an exponential function of -0.5R/Z where R is the wire resistance and Z is the characteristic impedance of the transmission line [1-3]. For a typical global wire, the impedance Z is around 40 ohms. For example, to set the attenuated ratio no less than 0.05, the wire resistance has to be less than 2Zln(1/0.05), i.e. R<= 240 ohms. Correspondingly, for a differential pair of 7mm, 5mm, or 1mm length, the cross section is supposed to be no less than 1, 0.7, or 0.14 square um, respectively. Note that we approximate the feature sizes with simple expressions by ignoring factors such as proximity and skin effects. 2. The intersymbol interference: We need to solve the intersymbol interference caused by the signal distortion. Following the attenuated wave front, the signal keeps in rising to a saturated voltage. The slow rising wave interferes with the signals in other time slots. In order to remove the interference, we have to compensate the distortion. We can preemphasize the signal at the driver or equalize at the receiver to increase the magnitude in high frequency band [2,11]. The compensation can be carried out by active devices or even passive RLC components [6,7,10] to save power. Moreover, we can add shunts along the wire to alleviate signal distortion [8,9]. Deliberation for the best choices can significantly improve the quality of the interconnect for the desired applications. 3. The performance of drivers and receivers: The delay and bandwidth of the drivers and receivers contribute to the overall performance of the interconnect. Currently, the delay of drivers and receivers dominates the interconnect. For a voltage-source driver, the terminated resistor has to match the characteristic impedance of the transmission line. At the receiver, we need a sense amplifier to recover the signal to full swing. The required conversion at the drivers and receivers contributes to the delay and bandwidth limit. Fortunately, as technology scales, the device performance will improve. We will find a window of technology nodes which provide an optimal spot for on-chip transmission lines to outperform segmented RC wires with repeated buffers. 4. The scalability: We would like to shrink the transmission lines to increase the throughput of the communication in a given physical space. As noted in item 1, the cross section is related to the length of the wire. We can use inserted transceivers to reduce the wire length. The insertion will then scale the cross section of the wires at the expense of extra power consumption. At first, special signal distributions such as clocks and buses are good candidates for on-chip transmission line technologies. Once the technologies are mature, general applications to global signals will follow. [1] H. Johnson and M. Graham, High-Speed Signal Propagation, Prentice Hall, 2003. [2] W.J. Dally, J.W. Poulton, Digital Systems Engineering, Cambridge University Press, 1998. [3] C.K. Cheng, J. Lillis, S. Lin, N. Chang, Interconnect Analysis and Synthesis, John-Wiley, 2000. [4] L. Zhang, H. Chen, B. Yao, K. Hamilton, and C.K. Cheng, "Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power and Bandwidth Metrics under Different Design Goals," IEEE Int. Symp. on Quality Electronic Design, 2007, pp. 251--256. [5] M. Lai and D.F. Wong, "Maze Routing with Buffer Insertion and Wiresizing," IEEE Trans. on Computer-Aided Design, Oct. 2002, pp. 1205-1209. [6] M. Flynn and J. Kang, "Global Signaling over Lossy Transmission Lines," IEEE/ACM Int. Conf. on Computer-Aided Designs, Nov. 2005, pp. 985--992. [7] A. Tsuchiya, M. Hashimoto, and H. Onadera, "Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects," IEEE Custom Integrated Circuits Conf., Sept. 2005, pp. 613--616. [8] H. Chen, R. Shi, and C.K. Cheng, "Surfliner: A Distortionless Electrical Signaling Scheme for Speed-of-Light On-Chip Communication," IEEE Int. Conf. on Computer Design, Oct. 2005, pp. 497--502. [9] H. Zhu, R. Shi, C.K. Cheng, and H. Chen, "Approaching Speed-of-Light Distortionless Communication for On-Chip Interconnect," Asia and South Pacific Design Automation Conf., Jan. 2007, pp. 684--689. [10] C.C. Liu, H. Zhu, and C.K. Cheng, "Passive Compensation for High Performance Inter-Chip Communication," IEEE Int. Conf. on Computer Design, Oct. 2007, pp. 547--552. [11] B. Kim and V. Stojanovic, "Equalized Interconnects for On-Chip Networks: Modeling and Optimization Framework," IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 552-559, 2007. ============================================================================== Paper Submission Deadlines: ---------------------------- ICST'08 - Int'l Conference on Sensing Technology Tainan, Taiwan Nov 30.Dec 3, 2008 Deadline: Jul 15, 2008 (extended) http://conf.ncku.edu.tw/icst2008/ VLSI'09 - Int'l Conference on VLSI Design New Delhi, India Jan 8-12, 2009 Deadline: Jul 17, 2008 http://vlsiconference.com/vlsi2009/ DATE'09 - Design Automation and Test in Europe (sponsored by SIGDA) Nice, France Apr 20-24, 2009 Deadline: Sep 7, 2008 http://www.date-conference.com/ ISCAS'09 - Int'l Symposium on Circuits and Systems Taipei, Taiwan May 24-27, 2009 Deadline: Oct 10, 2008 http://iscas2009.org/ ============================================================================== Upcoming Symposia, Conferences and Workshops: --------------------------------------------- MWSCAS'08 - Int'l Midwest Symposium on Circuits and Systems Knoxville, TN Aug 10-13, 2008 http://www.eecs.utk.edu/mwscas/ ISLPED'08 - Int'l Symposium on Low Power Electronics and Design Bangalore, India Aug 11-13, 2008 http://www.islped.org/ PDCS'08 - Int'l Conference on Parallel and Distributed Computing Systems Singapore Aug 29-31, 2008 http://www.waset.org/pdcs08/ SBCCI'08 - Symposium on Integrated and Systems Design (sponsored by SIGDA) Gramado, Brazil Sep 1-4, 2008 http://www.inf.ufrgs.br/chipinthepampa2008/sbcci.php DSD'08 - Euromicro Conference on Digital System Design Parma, Italy Sep 3-5, 2008 http://dsd08.iet.unipi.it/index.htm FPL'08 - Int'l Conference on Field-Programmable Logic and Applications Heidelberg, Germany Sep 8-10, 2008 http://www.kip.uni-heidelberg.de/fpl08/cms/website.php PATMOS'08 - Power and Timing Modeling, Optimization & Simulation Lisbon, Portugal Sep 10-12, 2008 http://algos.inesc-id.pt/patmos/home.shtml?general CICC'08 - Custom Integrated Circuits Conference San Jose, CA Sep 21-24, 2008 http://www.ieee-cicc.org/ VLSI-SoC'08 - Int'l Conference on Very Large Scale Integration Rhodes Island, Greece Oct 13-15, 2008 http://vlsi.ee.duth.gr/vlsisoc-2008/ CODES+ISSS'08 - Int'l Conference on Hardware-Software Codesign and System Synthesis (sponsored by SIGDA) Atlanta, GA Oct 19-24, 2008 http://www.codes-isss.org/ PACT'08 - Int'l Conference on Parallel Architectures and Compilation Techniques Toronto, Canada Oct 25-29, 2008 http://www.eecg.toronto.edu/pact/ ICCAD'08 - Int'l Conference on Computer-Aided Design (sponsored by SIGDA) San Jose, CA Nov 10-13, 2008 http://www.iccad.com/ MICRO'08 - Int'l Symposium on Microarchitecture Lake Como, Italy Nov 8-12, 2008 http://www.microarch.org/micro41/ ICPADS'08 - Int'l Conference on Parallel and Distributed Systems Melbourne, Australia Dec 8-10, 2008 http://www.deakin.edu.au/conferences/icpads2008/ EUC'08 - Int'l Conference on Embedded and Ubiquitous Computing Shanghai, China Dec 17-20, 2008 http://epcc.sjtu.edu.cn/euc2008/ HiPC'08 - Int'l Conference on High Performance Computing Bangalore, India Dec 17-20, 2008 http://www.hipc.org/ HiPEAC'09: Int'l Conference on High Performance Embedded Architectures & Compilers Paphos, Cyprus Jan 25-28, 2009 http://www.hipeac.net/conference =============================================================================== Upcoming Funding Opportunities ---------------------------------- DOE Advanced Scientific Computing Research (ASCR) (DE-PS02-08ER08-01) Deadline: September 30, 2008 http://www.science.doe.gov/grants/FAPN08-01.html DOD Military Networking Technology for Global Information Exchange (GIE) Deadline: Continuous until September, 2008 http://fedbizopps.cos.com/cgi-bin/getRec?id=20040909a11 Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html SPINS in Semiconductors Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Artificial Intelligence Technologies Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Quantum Information Science and Technology Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Microsystems Technology Office-Wide Deadline: January 14, 2009 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html Modeling and Simulation for Information Systems Research Deadline: FY 10 should be submitted by June 1, 2009 http://fedbizopps.cos.com/cgi-bin/getRec?id=20061030a9 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.rdecom.army.mil/STTC/2006_N61339-05-R-0095__BAA_FY06_Amendment_0001.pdf Army Research Office (ARO) Broad Agency Announcement for Basic and Applied Scientific Research (W911NF-07-R-0003) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 ARL/ARO Core Broad Agency Announcement for Basic and Applied Scientific Research for Fiscal Years 2007 through 2011 (W911NF-07-R-0001) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 NSF Expeditions in Computing Deadline: Letter of Intent Due Date(s) (required): July 10, 2008 July 10, Annually Thereafter Preliminary Proposal Due Date(s) (required): September 10, 2008 September 10, Annually Thereafter http://www.nsf.gov/pubs/2007/nsf07592/nsf07592.htm Faculty Early Career Development (CAREER) Program Deadline: July 22, 2008 http://nsf.gov/funding/pgm_summ.jsp?pims_id=503214&org=CISE&from=home CISE Computing Research Infrastructure (CRI) - NSF 06-597 Deadline: August 05, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=12810 NSF Scholarships in Science, Technology, Engineering, and Mathematics (S-STEM) - NSF 07-524 Deadline: August 12, 2008 http://www.nsf.gov/pubs/2007/nsf07524/nsf07524.htm Strategic Technologies for Cyberinfrastructure (STCI) Deadline: August 14, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500066 Instrument Development for Biological Research (IDBR) - NSF 07-568 Deadline: August 29, 2008 http://www.nsf.gov/pubs/2007/nsf07568/nsf07568.htm CreativeIT - NSF 08-572 Deadline: September 26, 2008 http://www.nsf.gov/pubs/2008/nsf08572/nsf08572.htm Engineering Design and Innovation (EDI) Deadline: October 1, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13340 Information and Intelligent Systems (IIS): Core Programs Deadline: Medium Projects October 1, 2008 - October 31, 2008 Large Projects November 1, 2008 - November 28, 2008 Small Projects December 1, 2008 - December 17, 2008 http://www.nsf.gov/div/index.jsp?div=IIS Computing and Communication Foundations (CCF): Core Programs Deadline: Medium Projects October 1, 2008 - October 31, 2008 Large Projects November 1, 2008 - November 28, 2008 Small Projects December 1, 2008 - December 17, 2008 http://www.nsf.gov/pubs/2008/nsf08577/nsf08577.htm#pgm_desc_txt Collaborative Research in Computational Neuroscience (CRCNS) Deadline: February 26, 2008 October 30, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=5147&org=CISE&from=home High Performance Computing Acquisition: Towards a Petascale Computing Environment for Science and Engineering - NSF 05-625 Deadline: November 28, 2008 http://www.nsf.gov/pubs/2005/nsf05625/nsf05625.htm Sloan Foundation Sloan Research Fellowships Deadline: September 15, 2008 http://www.sloan.org/programs/scitech_fellowships.shtml ============================================================================== Call For Nominations ---------------------- 2008 ACM Outstanding Ph.D. Dissertation Award in EDA http://www.sigda.org/opda.html Submission Deadline: September 15, 2008 Award Description: Design automation has gained widespread acceptance by the VLSI circuits and system design community. Advancements in computer-aided design (CAD) methodologies, algorithms, and tools have become increasingly important to cope with the rapidly growing design complexity, higher performance and low-power requirements, and shorter time-to-market demands. To encourage innovative, ground-breaking research in the area of electronic design automation, the ACM's Special Interest Group on Design Automation (SIGDA) has established an ACM award to be given each year to an outstanding Ph.D. dissertation that makes the most substantial contribution to the theory and/or application in the field of electronic design automation. The award consists of a certificate and a check for $1,000 and is presented at the Design Automation Conference, which is held in June/July of each year. The award is selected by a committee of experts from academia and industry in the field and appointed by ACM in consultation with the SIGDA Chair. Nomination requirements and procedure: * Each department of any university may nominate at most TWO Ph.D. dissertations with final submission date between July 1st of the previous year and June 30th of the current year. * Each nomination package must be emailed by September 15 and should consist of: 1. The PDF file of the Ph.D. dissertation. 2. A statement (up to two pages) from the nominee explaining the significance and major contributions of the work. 3. A nomination letter from nominee's department chair or dean of the school endorsing the application. 4. Optionally, up to three additional letters of recommendation from experts in the field. These letters may be included in the package or sent separately to the address below. The nomination materials should be emailed to Prof. Radu Marculescu at: radum@ece.cmu.edu (Subject: ACM Outstanding Ph.D. Dissertation Award in EDA). ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ============================================================================== This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To unsubscribe, send an email to listserv@listserv.acm.org with "signoff sigada-announce" (no quotes) in the body of the message. Please make sure to send your request from the same email as the one by which you are subscribed to the list. ==============================================================================