=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membership. Circulation: 2,700 =============================================================================== 15 May 2008 ACM/SIGDA E-NEWSLETTER Vol. 38, No. 10 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Soheil Ghiasi Contributing author: Matthew Guthaus Contributing author: Umit Y Ogras Contributing author: Marc Riedel Contributing author: Lin Yuan (2) What is Post-Silicon Debug? Author: Igor Markov From: Deming Chen (3) Paper Submission Deadlines From: Debjit Sinha (4) Upcoming Conferences and Symposia From: Debjit Sinha (5) Upcoming Funding Opportunities From: Qinru Qiu (6) Call For Papers: IEEE Computer Architecture Letters From: Kevin Skadron Debjit Sinha =============================================================================== Dear ACM/SIGDA members, We have reprinted the "What Is ..." column from the last newsletter. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Qing Wu, E-Newsletter Editor; Matthew Guthaus, E-Newsletter Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Debjit Sinha, E-Newsletter Associate Editor; Lin Yuan, E-Newsletter Associate Editor; Soheil Ghiasi, E-Newsletter Associate Editor; Deming Chen, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "Embedded Software Development Tools Make For More Flexible Silicon" http://www.edn.com/article/CA6558499.html Evolving approaches to software development go beyond simply making processor-based design faster and easier. An emerging trend sees vendors making hardware more flexible and providing software that allows designers to more easily explore options and move among processing choices. "IBM Brings HPC to the Masses With Next-Gen Cell Processor" http://www.edn.com/article/CA6560459.html Thanks to its PowerXCell 8i processor, which promises five-times the speed of the original Cell/B.E. processor for the most challenging arithmetic operations, IBM is bringing high performance computing to new application areas. "Mentor Graphics Acquires NXP Design-For-Test Technology, Developers" http://www.edn.com/article/CA6557850.html The EDA company gains the rights to NXP-developed DFT technologies and an undisclosed number of NXP developers. "Embedded Standards Become Critical" http://www.edn.com/blog/1710000171/post/1190026319.html As promised when the doors were closed on the long running Bus and Board conference, VITA (VMEbus International Trade Association) brought back a revised board-level meeting this week based on "critical embedded systems". These are life-critical or safety-critical systems whose failure or malfunction may result in death or serious injury, equipment damage, environmental harm, or large financial losses. "TSMC Announces Entry Into MEMS Market" http://sst.pennnet.com/display_article/327733/5/ARTCL/none/none/1/TSMC-announces-entry-into-MEMS-market/ Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has unveiled plans to enter the MEMS business, presenting a roadmap of the MEMS process and desires to cover trends in MEMS production at "CMOS integrated MEMS foundries," according to Nikkei Microdevices magazine, citing comments from a press meeting last week. A more detailed version will be presented later this month. "Mentor Graphics + Ponte: "End of the DFM dream" http://sst.pennnet.com/display_article/328861/5/ARTCL/none/none/1/Mentor-Graphics-+-Ponte:- The acquisition of DFM firm Ponte Solutions by EDA firm Mentor Graphics not only takes one of the last pure DFM companies off the table, it also answers the question about what side of the chipmaking wall DFM belongs, and terminates an inflection point that might not be seen again for a decade or more. "Lab-on-a-Chip Made of Paper" http://www.technologyreview.com/Biotech/20771/ Paper-based microfluidic devices could yield cheap, disposable diagnostic tests. By taking advantage of the natural movement of liquid through paper, researchers at Harvard's Whitesides Research Group may have found a way to make microfluidics technology much cheaper. The result could be disposable diagnostic tests simple and abundant enough for use in the developing world. =============================================================================== What is Post-Silicon Debug? ------------------------------- Author: Igor Markov Due to the complexity of modern IC designs and increasingly sophisticated manufacturing technologies, some of the steps in the design and optimization of ICs result in errors. A prime example of a design error is the Pentium IV FDIV bug --- a miscalculation when dividing certain rarely-occurring numbers, --- which resulted in the costly recalls of millions of CPUs in mid-1990s. Only rare errors escape extensive simulation used to verify designs, but they may jeopardize mission-critical applications and lead to class-action lawsuits. Some computer viruses escalate and exploit subtle hardware errors. Intel's response to the FDIV bug was to invest heavily in formal verification, so as to catch even the bugs that evade simulation. While very successful, this effort has always been limited to individual on-chip modules rather than entire chips. If bugs arising from the interaction between modules are not caught by extensive simulation, they show up in manufactured chips. The numbers of serious bug escapes have been growing --- they have led to CPU lock-ups, threats to OS security, and corrupted data. It was pointed out that logic simulation performed before tape-out runs several orders of magnitude slower than the actual chip. Therefore, major CPU vendors now first produce several test chips, stress-test them to find bugs, and then fix bugs before large-scale production runs. This stress-testing process is often called post-silicon validation, while the diagnosis and bug-fixing are collectively called post-silicon debugging. Manufacturing a new chip from corrected masks is often called a respin. Fabless semiconductor companies cannot usually afford many respins because a 65nm mask set may cost several million dollars. However, multiple respins (sometimes half a dozen) have become the norm for mass-produced CPUs. Even successful chips are often finetuned for better performance, lower power, standards compliance, market customization, and new manufacturing process. Post-silicon debug seeks to minimize the cost of mask alternation during bug-fixing by preserving the most expensive masks. For example, for a 65-nm manufacturing process with ten layers of metal, only four or five out of forty different masks support 65-nm features, while some exhibit only 90-nm features and some are even coarser. Since transistor-level masks are the most expensive, bug-fixes that change only wires and vias are desired, and termed metal-fix. Functional errors discussed above constitute only a fraction of problems observed in test chips, and are usually the easiest to handle because they can be reproduced in logic simulators. Electrical and thermal errors are often more insidious. In a common scenario, the delay of some circuit element may deviate from what was expected (e.g., due to crosstalk noise), preventing a signal transition from reaching a register before the end of the clock cycle. In other words, electrical aberrations or temporary overheating in the circuit trigger a delay error, which manifests as a functional error in registers. Such physical fluctuations may require a rare combination of data in registers, and may not equally affect every chip, due to process variability. Therefore, finding the root cause of a delay error sometimes takes a determined Sherlock Holmes, a well-stocked laboratory with expensive equipment, and weeks of dedicated labor. When a validation team catches an error in a test chip, they report it to a debugging team, along with physical conditions (supply voltage, clock frequency, ambient temperature) and the bug trace -- a sequence of stimuli that triggered the bug. It is now common to also report sensitivities to physical parameters by means of building a "shmoo" plot. A traditional voltage-frequency shmoo is a two-dimensional plot with marks "Passed" or "Failed" for every combination of X and Y parameters. The shape of the shmoo often suggests whether set-up or hold constraints were violated (slowing down the clock may fix set-up violations, while speeding it up may fix hold violations). If the delay error appears very sensitive to temperature, it is more likely to originate in transistors because wire delays rarely exhibit such sensitivities. Depending on the ability to reproduce the bug in a functional or electrical simulator, very different techniques may have to be utilized. For further details, we refer the reader to recent work from Intel on speedpath analysis [1] and from the University of Michigan on automated bug-fixing [2]. These techniques differ from those developed by the circuit-test community because test chips may suffer from poor observability of internal signals, and in some cases can only be controlled by running valid software programs on them (the actual levels of controllability vary dramatically between, e.g., Intel and IBM). A number of industry efforts address the problem of poor observability by integrating reconfigurable diagnostics circuits onto the chip. The reader may find additional details on Web pages of DAFCA's Clear Blue product [3] and Synplicity's Confirma product [4]. Post-Silicon validation and debug have recently become major bottlenecks in the design of large chips. They are now consuming 30-40% of the time to market, and leading-edge semiconductor companies employ thousands of people in respective divisions. Since most of the work is still done manually, great opportunities exist in research on post-Silicon validation and debug, as well as in entrepreneurial activities [5]. References [1] K. Killpack, C. V. Kashyap, and E. Chiprout, "Silicon Speedpath Measurement and Feedback into EDA flows," DAC 2007, pp. 390-395. [2] K-H. Chang, I.L. Markov, and V. Bertacco, "Automating Post-Silicon Debugging and Repair," ICCAD 2007, pp. 91-98. [3] DAFCA Clear Blue, http://www.dafca.com/products/clearblue.php [4] Synplicity Confirma, http://www.synplicity.com/products/prototyping_solutions.html [5] R. Goering, "Post-silicon debugging worth a second look," EE Times, http://www.eetimes.com/showArticle.jhtml?articleID=197002823 =============================================================================== Paper Submission Deadlines: ---------------------------- MICRO'08 - Int'l Symposium on Microarchitecture Lake Como, Italy Nov 8-12, 2008 Deadline: May 20, 2008 (Abstract submission deadline: May 13, 2008) http://www.microarch.org/micro41/ EUC'08 - Int'l Conference on Embedded and Ubiquitous Computing Shanghai, China Dec 17-20, 2008 Deadline: May 30, 2008 http://epcc.sjtu.edu.cn/euc2008/ ICM'08 - Int'l Conference on Microelectronics (technically co-sponsored by IEEE-VSATC) Sharjah, UAE Dec 14-16, 2008 Deadline: Jun 1, 2008 (extended) http://www.ieee-icm.com/ ICFPT'08 - Int'l Conference on Field-Programmable Technology Taipei, Taiwan Dec 8-10, 2008 Deadline: Jun 9, 2008 http://vda.ee.nctu.edu.tw/ICFPT/FPT08.htm ICPADS'08 - Int'l Conference on Parallel and Distributed Systems Melbourne, Australia Dec 8-10, 2008 Deadline: Jun 20, 2008 http://www.deakin.edu.au/conferences/icpads2008/ HiPEAC'09: Int'l Conference on High Performance Embedded Architectures & Compilers Paphos, Cyprus Jan 25-28, 2009 Deadline: Jul 4, 2008 http://www.hipeac.net/conference/ ASP-DAC'09 - Asia and South Pacific Design Automation Conference (sponsored by SIGDA) Yokohama, Japan Jan 19-22, 2009 Deadline: Jul 14, 2008 http://www.aspdac.com/aspdac2009/ VLSI'09 - Int'l Conference on VLSI Design New Delhi, India Jan 8-12, 2009 Deadline: Jul 17, 2008 http://vlsiconference.com/vlsi2009/ ============================================================================== Upcoming Symposia, Conferences and Workshops: --------------------------------------------- ISCAS'08 - Int'l Symposium on Circuits and Systems Seattle, WA May 18-21, 2008 http://iscas2008.org/ EWME'08 - European Workshop on Microelectronics Education Budapest, Hungary May 28-30, 2008 http://www.eet.bme.hu/new/index.php?option=com_content&task=view&id=129&Itemid=160 ICICDT'08 - Int'l Conference on IC Design & Technology Minatec in Grenoble, France Jun 2-4, 2008 http://www.icicdt.org/ RSP'08 - Int'l Workshop on Rapid System Prototyping Monterey, CA Jun 2-5, 2008 http://www.rsp-workshop.org/ ICAC'08 - Int'l Conference on Autonomic Computing Chicago, IL Jun 2-6, 2008 http://www.acis.ufl.edu/~icac2008/ IWLS'08 - Int'l Workshop on Logic & Synthesis San Diego, CA Jun 4-6, 2008 http://www.iwls.org/ MEMOCODE'08 - Int'l Conference on Formal Methods and Models for Codesign (sponsored by SIGDA) Anaheim, CA Jun 5-7, 2008 http://svl1.cs.pdx.edu/memocode08/ DAC'08 - Design Automation Conference (sponsored by SIGDA) Anaheim, CA Jun 9-13, 2008 http://www.dac.com/ PESPMA.08 - Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures, in conjunction with ISCA.08 - International Symposia on Computer Architecture Beijing, China Jun 22, 2008 http://cccp.eecs.umich.edu/pespma ACSD'08 - Int'l Conference on Application of Concurrency to System Design Xi.an, China Jun 23-27, 2008 http://ictt.xidian.edu.cn/acsd2008/Pages/ACSD_main.jsp ASAP'08 - Int'l Conference on Application-specific Systems, Architectures and Processors Leuven, Belgium July 2-4, 2008 http://asap-conference.org/ CAV'08 - Int'l Conference on Computer Aided Verification Princeton, NJ Jul 7-14, 2008 http://www.princeton.edu/cav2008/ ============================================================================== Upcoming Funding Opportunities ---------------------------------- DHS Center of Excellence for Command, Control and Interoperability Deadline: Jun 15, 2008 http://www07.grants.gov/search/search.do?&mode=VIEW&flag2006=false&oppId=41461 ACM Doctoral Dissertation Award Deadline: Sep 30, 2008 http://awards.acm.org/html/dda.cfm SRC Modeling & Simulation of Nanoelectronic Materials, Processes, and Devices Deadline: June 16, 2008 http://grc.src.org/fr/S200803_Call.asp NASA Applied Information Systems Research Deadline: July 23, 2008 http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId=%7B6FE1E776-C046-383D-8475-62A73BECFA4C%7D&path=open DOC Electronics and Electrical Engineering (EEEL) Grants Program Deadline: June 15, 2008 http://origin.www.gpoaccess.gov/fr/. (The full call can be located by searching the Federal Register for "fr25ja08N Measurement, Science and Engineering Grants Programs." ) DOE Advanced Scientific Computing Research (ASCR) (DE-PS02-08ER08-01) Deadline: September 30, 2008 http://www.science.doe.gov/grants/FAPN08-01.html DOD Modeling and Simulation for Information Systems Research Deadline: FY 09 should be submitted by June 1, 2008 FY 10 should be submitted by June 1, 2009 http://fedbizopps.cos.com/cgi-bin/getRec?id=20061030a9 Military Networking Technology for Global Information Exchange (GIE) Deadline: Continuous until September, 2008 http://fedbizopps.cos.com/cgi-bin/getRec?id=20040909a11 Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html SPINS in Semiconductors Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Artificial Intelligence Technologies Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Quantum Information Science and Technology Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Microsystems Technology Office-Wide Deadline: January 14, 2009 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.rdecom.army.mil/STTC/2006_N61339-05-R-0095__BAA_FY06_Amendment_0001.pdf Army Research Office (ARO) Broad Agency Announcement for Basic and Applied Scientific Research (W911NF-07-R-0003) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 ARL/ARO Core Broad Agency Announcement for Basic and Applied Scientific Research for Fiscal Years 2007 through 2011 (W911NF-07-R-0001) Deadline: Continuous through September 30, 2011 http://www.arl.army.mil/www/default.cfm?Action=6&Page=8 NSF Expeditions in Computing Deadline: Letter of Intent Due Date(s) (required): July 10, 2008 July 10, Annually Thereafter Preliminary Proposal Due Date(s) (required): September 10, 2008 September 10, Annually Thereafter http://www.nsf.gov/pubs/2007/nsf07592/nsf07592.htm Faculty Early Career Development (CAREER) Program Deadline: July 22, 2008 http://nsf.gov/funding/pgm_summ.jsp?pims_id=503214&org=CISE&from=home CISE Computing Research Infrastructure (CRI) - NSF 06-597 Deadline: August 05, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=12810 NSF Scholarships in Science, Technology, Engineering, and Mathematics (S-STEM) - NSF 07-524 Deadline: August 12, 2008 http://www.nsf.gov/pubs/2007/nsf07524/nsf07524.htm Strategic Technologies for Cyberinfrastructure (STCI) Deadline: August 14, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500066 Instrument Development for Biological Research (IDBR) - NSF 07-568 Deadline: August 29, 2008 http://www.nsf.gov/pubs/2007/nsf07568/nsf07568.htm Collaborative Research in Computational Neuroscience (CRCNS) Deadline: February 26, 2008 October 30, 2008 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=5147&org=CISE&from=home High Performance Computing Acquisition: Towards a Petascale Computing Environment for Science and Engineering - NSF 05-625 Deadline: November 28, 2008 http://www.nsf.gov/pubs/2005/nsf05625/nsf05625.htm Sloan Foundation Sloan Research Fellowships Deadline: September 15, 2008 http://www.sloan.org/programs/scitech_fellowships.shtml ============================================================================== Call for papers: ---------------- IEEE Computer Architecture Letters IEEE Computer Architecture Letters seeks submissions from the SIGDA community. IEEE CAL is a forum for fast publication of new, high-quality ideas in the form of short (4-page), critically refereed, technical papers. Decisions are returned within one month of submission. Submissions on any aspect of computer architecture are accepted on a continuing basis, and accepted letters will be published immediately in IEEE Xplore and the IEEE Computer Society Digital Library, and in the next available print issue. Current acceptance rate is about 25%. For more details, see: http://www.comp-arch-letters.org For questions, feel free to contact Kevin Skadron or Jean-Luc Gaudiot - To subscribe to an RSS feed of CAL papers in the Computer Society Digital Library (includes preprints): http://csdl.computer.org/rss/cal.xml - To subscribe to an RSS feed of tables of contents of new print issues in Xplore (Xplore publishes preprints but does not include them in its RSS feed): http://ieeexplore.ieee.org/rss/TOC10208.XML ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ============================================================================== This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To unsubscribe, send an email to listserv@listserv.acm.org with "signoff sigada-announce" (no quotes) in the body of the message. Please make sure to send your request from the same email as the one by which you are subscribed to the list. ==============================================================================