=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membersip. Circulation: 2,700 =============================================================================== 15 May 2007 ACM/SIGDA E-NEWSLETTER Vol. 37, No. 10 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What is Plasmonics? Author: Harry A. Atwater, CalTech From: Igor Markov (3) Paper Submission Deadlines From: Hai Zhou (4) Upcoming Conferences and Symposia From: Hai Zhou (5) Upcoming Funding Opportunities From: Qinru Qiu (6) Table of Content : ACM TODAES (7) Call for Papers : PhD Forum of 2007 VLSI-SoC From: Matthew Guthaus (8) Call for Papers : ASP-DAC 2008 From: Hai Zhou (9) Call for Papers : IEEE Computer Architecture Letters From: Hai Zhou (10) Call For Papers : Special Issue on Demonstrable Software Systems and Hardware Platforms II From: Alex K. Jones =============================================================================== Dear ACM/SIGDA members, In this issue, we have included the table of content for the newest issue of ACM Transactions on Design Automation of Electronic Systems (TODAES). The "What is ..." column in the previous newsletter is reprinted. In addition, the "SIGDA News" column contains a number of fresh headlines. We have also updated the contents of other regular columns. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Tony Givargis, E-Newsletter Associate Editor; Matthew Guthaus, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "Cadence Buys U.C. Berkeley DFM Spinoff" http://www.eetimes.com/showArticle.jhtml?articleID=199501788 The jump from academia to the commercial EDA world happened quickly for three graduate students from the University of California at Berkeley, who developed technology and a business plan that resulted in a design for manufacturability (DFM) startup that was just purchased by Cadence Design Systems. Cadence has confirmed its purchase of DFM startup CommandCAD, a provider of IC layout optimization technology that claims to boost yields and improve optical proximity correction (OPC). "CommandCAD solves a particular problem and solves it very well," Keutzer, Professor of EECS at UC Berkeley said. Its core technology, he said, can find "families" of patterns in IC physical layouts that can cause yield problems. That's a slow process with today's design rule checking tools, he said. A side benefit is the ability to decompose layouts into regular patterns. This could have applications in such areas as lithography simulation, Keutzer said. "Extreme Low-Power Design" http://www.edn.com/index.asp?layout=article&articleid=CA6437957 A typical modern pacemaker may consume on average only a few microamperes of current to achieve long battery life. To meet these low power requirements, engineers use many techniques that may be applicable today to other power-conscious designs. The techniques vary from analog to digital and from circuit to system level, all of which are necessary to keep power to such a minimum. "Cooling Superfast Computer Chips With Carbon Nanotubes" http://www.azonano.com/Details.asp?ArticleID=1899 As computer chips get smaller and smaller, advances in technology are also making them increasingly faster. These speed increases require more power and this power is being pumped into smaller and smaller areas. The power is mostly dissipated as heat but concentrating intense amounts of heat in such a small area causes problems. "Nanoscale Pasta: Toward Nanoscale Electronics" http://nanotechwire.com/news.asp?nid=4668 Pasta tastes like pasta - with or without a spiral. But when you jump to the nanoscale, everything changes: carbon nanotubes and nanofibers that look like nanoscale spiral pasta have completely different electronic properties than their non-spiraling cousins. Engineers at UC San Diego, and Clemson University are studying these differences in the hopes of creating new kinds of components for nanoscale electronics. "Executable Biology -- Computer Science Sheds Light on Animal Development" http://www.eurekalert.org/pub_releases/2007-05/plos-ebc051607.php By applying the techniques of computer engineering to a mechanistic diagram describing the development of the Nematode C. elegans, a group of researchers in Switzerland has been able to tease out what laboratory experiments have not - how and when the crucial cross-talk between cellular signaling pathways takes place in order to determine the fates of individual cells. The novel in silico model is described in a paper appearing May 18, 2007 in the open-access journal PLoS Computational Biology. "Understanding Patents: How to Be Prepared for Due Diligence" http://www.edn.com/article/CA6438583.html With the proliferation of alliances, acquisitions, investments, and deals and fundraising activities in general in today's technology climate, any technology business entity has a likelihood of enduring at least one due diligence review. "Circuit Is Missing Link in Quantum Computing" http://www.electronicstalk.com/news/nei/nei105.html Technology achieving control of the coupling strength between qubits is vital to the realisation of a practical quantum computer, and has been long awaited in the scientific field. The quantum computer, when it is finally brought to fruition, is expected to far surpass the capabilities of even the most modern of today's supercomputers. "TI Takes Two Approaches to IC Manufacturing" http://www.eetimes.com/showArticle.jhtml?articleID=199500883 Moving to remain competitive in what has become a brave new world of IC manufacturing, Texas Instruments Inc. last week disclosed the details of its revised "hybrid" fab strategy. The chip maker is bolstering its in-house efforts in analog production, but it is also shifting more of its logic-based IC work and process flow to the foundries. As a result of the shift, TI has pushed out the production ramp date for its new--and still unequipped--300-mm fab in Texas by about 18 months.Nearly half of TI's logic chip production is outsourced to the foundries today, but that figure could jump to 70 percent over time, according to analysts. TI says it has no intention of going fabless for logic. But the chip maker's foundry partners for the 45-nanometer node--TSMC, UMC and a yet-to-be-determined vendor--will play a much bigger role than TI has afforded foundries in the past. And by 32 nm, TI will co-develop its processes at the foundries, whereas traditionally it has done that work in-house. "Telecommuting" http://www.embedded.com/shared/printableArticle.jhtml?articleID=199501650 Telecommuting still has a small presence in the embedded space. Why? Last week CIO magazine ran an article titled: "Getting Clueful: Seven Things the CIO Should Know About Telecommuting." It's a short and pithy piece that contains some excellent advice for any boss who is either reluctant to try telecommuting, and for those flirting with a pilot program. "Optimized Memory Utilization Boosts Graphics Display Controller IC Efficiency" http://www.embedded.com/shared/printableArticle.jhtml?articleID=199601784 Graphics display controllers (GDCs) are becoming very popular in an increasing range of embedded automotive electronics applications such as infotainment and navigation displays. "New-Generation Statistical Approach 65-nm and 45-nm Process Nodes" http://www.chipdesignmag.com/print.php?articleId=1315?issueId=0 Extreme DAearch Center (STARC) -- are collaborating to jointly develop and validate a variability-aware timing analysis flow for integrated circuits (ICs) manufactured in 65- and 45-nanometer (nm) processes. "Panasonic Introduces Next Generation Blu-Ray Disc Player" http://www.electronicdesign.com/yellowbrix/story.cfm?AD=1&AD=1&story_id=106353336 Panasonic, one of the industry leaders behind the development of Blu-ray Disc(TM) technology and the market leader in Plasma television, today announced the availability of the DMP- BD10A, Panasonic's next generation Blu-ray Disc player, at a SRP of $599.95. "Towards Scalable Design Tools" http://www.chipdesignmag.com/display.php?articleId=1317 Parallelism is changing the world. More specifically, parallelism is changing information technology and everything that depends on it. The driver has been for some time the hardware. In 2006, worldwide shipments of PC and x86 servers exceeded 239 million units. Cost effective "server farms" have been ubiquitous for many years. Since the advent of the first dual-core processor chip in 2001 (the IBM Power4), increasingly processors are becoming multi-core. The race for GigaHertz (GHz) has been largely overtaken by the race for multi-cores. ============================================================================== What is Plasmonics? -------------------------------- Harry A. Atwater, CalTech http://www.sciam.com/article.cfm?chanID=sa006&articleID=5BED2E76-E7F2-99DF-3A1C740338CE5666&ref=rss ============================================================================== Submission deadlines: --------------------- EUC'07 - Int'l Conference on Embedded and Ubiquitous Computing Taipei, Taiwan Dec 17-20, 2007 Deadline: May 24, 2007 (extended) http://www.cs.ccu.edu.tw/~shiwulo/euc07/ ICPADS'07 - Int'l Conference on Parallel and Distributed Systems Hsinchu, Taiwan Dec 5-7, 2007 Deadline: May 31, 2007 (extended) http://www.ccrc.nthu.edu.tw/icpads2007/ MICRO'07 - Int'l Symposium on Microarchitecture Chicago, IL Dec 1-5, 2007 Deadline: Jun 1, 2007 http://www.microarch.org/micro40/ HiPEAC'08: Int'l Conference on High Performance Embedded Architectures & Compilers Goteborg, Sweden Jan 27-29, 2008 Deadline: Jun 10, 2007 http://www.hipeac.net/hipeac2007/ ICM'07 - Int'l Conference on Microelectronics Cairo, Egypt Dec 29-31, 2007 Deadline: Jun 15, 2007 http://www.ieee-icm.com/ PDCS'07 - Int'l Conference on Parallel and Distributed Computing Systems Cambridge, MA Nov. 19-21, 2007 Deadline: Jun 15, 2007 http://www.iasted.org/conferences/home-590.html ICFPT'07 - Int'l Conference on Field-Programmable Technology Kitakyushu, Japan Dec 12-14, 2007 Deadline: Jun 25, 2007 http://www.kameyama.ecei.tohoku.ac.jp/icfpt07/ ICST'07 - Int'l Conference on Sensing Technology Palmerston North, New Zealand Nov 26-28, 2007 Deadline: Jun 29, 2007 http://icst.massey.ac.nz/ ASP-DAC'08 - Asia and South Pacific Design Automation Conference (sponsored by SIGDA) Seoul, Korea Jan 21-24, 2008 Deadline: Jul 10, 2007 http://www.aspdac.com/aspdac2008/ VLSI'08 - Int'l Conference on VLSI Design (sponsored by SIGDA) ES'08 - Int'l Conference on Embedded Systems Hyderabad, India Jan 4-8, 2008 Deadline: Jul 10, 2007 http://vlsiconference.com/vlsi2008/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- RSP'07 - Int'l Workshop on Rapid System Prototyping Porto Alegre, Brazil May 28-30, 2007 http://www.rsp-workshop.org/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 http://www.iess.org/ ICICDT'07 - Int'l Conference on IC Design & Technology Austin, TX May 30-Jun 1, 2007 http://www.icicdt.org/ MEMOCODE'07 - Int'l Conference on Formal Methods and Models for Codesign (sponsored by SIGDA) Nice, France May 30-Jun 1, 2007 http://memocode.irisa.fr/ IWLS'07 - Int'l Workshop on Logic & Synthesis (sponsored by SIGDA) San Diego, CA May 30-Jun 1, 2007 http://www.iwls.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 http://www.mseconference.org/ DAC'07 - Design Automation Conference (sponsored by SIGDA) San Diego, CA Jun 4-8, 2007 http://www.dac.com/ CAV'07 - Int'l Conference on Computer Aided Verification Berlin, Germany Jul 3-7, 2007 http://www.cav2007.org/ ASAP'07 - Int'l Conference on Application-specific Systems, Architectures and Processors Montreal, Canada July 9-11, 2007 http://asap-conference.org/ ACSD'07 - Int'l Conference on Application of Concurrency to System Design (Sponsored by SIGDA) Bratislava, Slovak Republic Jul 10-13 2007 http://www.acsd.sk/ MWSCAS/NEWCAS'07 - Int'l Midwest Symposium on Circuits and Systems/ Int'l NEWCAS Conference Montreal, Canada Aug 5-8, 2007 http://newcas.grm.polymtl.ca/ FPL'07 - Int'l Conference on Field-Programmable Logic and Applications Amsterdam, Holland Aug 27-29, 2007 http://www.fpl.uni-kl.de/fpl/ DSD'07 - Euromicro Conference on Digital System Design Lubeck, Germany Aug 29-31, 2007 http://www.dsdconf.org/ PATMOS'07 - Power and Timing Modeling, Opt. & Sim. Goteborg, Sweden Sep 3-5, 2007 http://www.ce.chalmers.se/research/conference/patmos07/ SBCCI'07 - Symposium on Integrated and Systems Design (sponsored by SIGDA) Rio de Janeiro, Brazil Sep 3-6, 2007 http://www.sbcci.pads.ufrj.br/sbcci/index_sbcci.html PACT'07 - Int'l Conference on Parallel Architectures and Compilation Techniques Brasov, Romania Sep 15-19, 2007 http://www.pactconf.org/ CICC'07 - Custom Integrated Circuits Conference San Jose, CA Sep 16-19, 2007 http://www.ieee-cicc.org/ CODES+ISSS'07 - Int'l Conference on Hardware-Software Codesign and System Synthesis (sponsored by SIGDA) Salzburg, Austria sep 30-Oct 5, 2007 http://www.codes-isss.org/ VLSI-SoC'07 - Int'l Conference on Very Large Scale Integration Atlanta, GA Oct 15-17, 2007 http://www.vlsisoc2007.gatech.edu/ ICCAD'07 - Int'l Conference on Computer-Aided Design (sponsored by SIGDA) San Jose, CA Nov 4-8, 2007 http://www.iccad.com/ HiPC'07 - Int'l Conference on High Performance Computing Goa, India Dec 18-21, 2007 http://www.hipc.org/ ============================================================================== Upcoming Funding Opportunities -------------------------------- World Community Grid Request for Proposals Deadline: June 30, 2007 http://www.worldcommunitygrid.org/projects_showcase/viewSubmitAProposal.do ACM Doctoral Dissertation Award Deadline: August 31, 2007 http://fundingopps.cos.com/alerts/33218?id=33218&if=alert NIH NLM Knowledge Management & Applied Informatics Grants Deadline: May 25, 2007 September 25, 2007 January 25, 2008 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-236.html Continued Development and Maintenance of Software (R01) Deadline: May 17, 2007 September 13, 2007 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-235.html NASA Applied Information Systems Research - NNH07ZDA001N-AISR Deadline: To be announced (TBA) http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId=%7B89FBF877-DD5F-AC6E-DAB3-AE19504EA70D%7D&path=open DOD Cognitive Technology Threat Warning System (CT2WS) Deadline: April 11, 2008 http://fedbizopps.cos.com/cgi-bin/getRec?id=20070412a1 Warrior Systems Technologies - Body-Worn Systems, Hand Held Devices, and Smart-Lightweight Electronic Components/Modules for Soldier Protection, Knowledge Management and Cognitive Improvement Deadline: Continuous. (April 1, 2007 ~ March 31, 2009) https://www3.natick.army.mil/ssbaa.htm Homeland Security (2.2.1) - N61339-02-R-0071 Deadline: Continuous. This BAA expires on January 30, 2008 http://www1.fbo.gov/spg/DON/NAVAIR/N61339/N61339-02-R-0071/Attachments.html Microsystems Technology Office-Wide Deadline: January 14, 2009 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html SPINS in Semiconductors Deadline: December 31, 2008 http://fundingopps.cos.com/alerts/57993 Artificial Intelligence Technologies Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/baa.htm Quantum Information Science and Technology Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Young Investigator Program (YIP) January 12, 2008 http://www.onr.navy.mil/sci_tech/3t/corporate/yip.asp High Density Optical Memory Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Quantum Electronic Solids Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Distributed Intelligence Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF CreateiveIT (NSF 07-562) Deadline: July 23, 2007 http://www.nsf.gov/pubs/2007/nsf07562/nsf07562.htm Accelerating Discovery in Science and Engineering Through Petascale Simulations and Analysis (PetaApps) - NSF 07-559 Deadline: July 23, 2007 http://www.nsf.gov/pubs/2007/nsf07559/nsf07559.htm Biological Databases and Informatics - NSF 05-577 Deadline: July 9, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=5444 DARPA Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm Sloan Foundation Sloan Research Fellowships Deadline: September 15, 2007 http://www.sloan.org/programs/scitech_fellowships.shtml ============================================================================== Table of Contents ------------------- ACM Transactions on Design Automation of Electronic Systems (TODAES) Volume 12 , Issue 2 (April 2007) Editorial Nikil Dutt http://portal.acm.org/ft_gateway.cfm?id=1230801&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Disjunctive image computation for software verification Chao Wang, Zijiang Yang, Franjo Ivanv.i., Aarti Gupta http://portal.acm.org/ft_gateway.cfm?id=1230802&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Transition-overhead-aware voltage scheduling for fixed-priority real-time systems Bren Mochocki, Xiaobo Sharon Hu, Gang Quan http://portal.acm.org/ft_gateway.cfm?id=1230803&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Prediction of leakage power under process uncertainties Hongliang Chang, Sachin S. Sapatnekar http://portal.acm.org/ft_gateway.cfm?id=1230804&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 A model-based extensible framework for efficient application design using FPGA Sumit Mohanty, Viktor K. Prasanna http://portal.acm.org/ft_gateway.cfm?id=1230805&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 A predictive decode filter cache for reducing power consumption in embedded processors Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau http://portal.acm.org/ft_gateway.cfm?id=1230806&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 DRDU: A data reuse analysis technique for efficient scratch-pad memory management Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt http://portal.acm.org/ft_gateway.cfm?id=1230807&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Low test application time resource binding for behavioral synthesis Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi http://portal.acm.org/ft_gateway.cfm?id=1230808&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 A critical-path-aware partial gating approach for test power reduction Mohammed Elshoukry, Mohammad Tehranipoor, C. P. Ravikumar http://portal.acm.org/ft_gateway.cfm?id=1230809&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 Forming N-detection test sets without test generation Irith Pomeranz, Sudhakar M. Reddy http://portal.acm.org/ft_gateway.cfm?id=1230810&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 The exact channel density and compound design for generic universal switch blocks Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung http://portal.acm.org/ft_gateway.cfm?id=1230811&type=pdf&coll=portal&dl=ACM&CFID=565653505&CFTOKEN=565653505 ============================================================================== Call for Papers ----------------- PhD Forum Call for Paper VLSI-SoC 2007 15-17 October 2007 Georgia Institute of Technology Altanta, Georgia, U.S.A. The PhD Forum at VLSI-SoC 2007 Conference is a poster session included as part of the conference program, aiming at the exchange of ideas and experiences of PhD students from different parts of the world. Elected PhD students will have an opportunity to discuss their thesis and research work with specialists within the system and design automation community. This offers a good opportunity for students to receive valuable feedback on their work and to gain exposure to the job market. Furthermore, this forum also provides a great chance for industry to meet junior researchers, giving the avenue for incorporating the latest research developments into their companies. *Eligibility The author must have completed at least one year of a PhD program. *Presentation Posters will be introduced in the PhD Forum Session (2 minute time slot, one slide) and next presented in a full one-hour Poster Session. *Publication Accepted abstracts will be published as papers (6 pages maximum) in a separate VLSI-SoC'07 PhD CD-ROM Proceedings. *Grants for PhD students VLSI-SoC 2007 finances a limited number of travel grants for PhD students, through the Technical Committee TC-10 (Computer Students Technology) of International Federation for Information Processing. In principle grants are restricted to support students that cannot be supported by their institutions. This rule gives preference to students being enrolled in Africa, Latin America, Eastern Europe including Russia, and Asia (except Israel, Japan, South Korea and Taiwan). The percentage covered by a grant should be at least 50% of the total costs. *How to Submit A one-page extended abstract of the dissertation plus one page for figures in PDF format. The one-page limit on the abstract text and figures will be strictly enforced. Send submission to waynecheng@mail.nctu.edu.tw before June 25, 2007. ============================================================================== Call for Papers ----------------- ASP-DAC 2008 Asia and South Pacific Design Automation Conference 2008 http://www.aspdac.com/aspdac2008/ January 21-24, 2008 COEX, Seoul, Korea Aims of the Conference: ASP-DAC 2008 is the thirteenth in a series of annual international conferences on VLSI design automation. Asia and South Pacific region is one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances in the technologies related to Electronic Design Automation (EDA) and discussing the future directions. The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. A wide variety of those scientists, engineers, and students who are interested in theoretical issues in EDA are also welcome. Areas of Interest: Original papers on, but not limited to, the following areas are invited. [1] System Level Design: System VLSI and SOC design methods, System specification, Specification languages, Design languages, Hardware-software co-design, Co-simulation, Co-verification, Platform-based design, Design reuse and IP's [2] Embedded and Real-Time Systems: Low power system design, Network on chip, Communication architecture, Memory architecture, Real-time OS and middleware, Compilation techniques, ASIP synthesis [3] Behavioral/Logic Synthesis and Optimization: Behavioral/RTL synthesis, Technology-independent optimization, Technology mapping, Interaction between logic design and layout, Sequential and asynchronous logic synthesis [4] Validation and Verification for Behavioral/Logic Design: Logic simulation, Symbolic simulation, Formal verification, Equivalence checking, Transaction-level/RTL and gate-level modeling and validation [5] Physical Design (Routing): Routing, Repeater issues, Interconnect optimization, Interconnect planning, Module generation, Layout verification [6] Physical Design (Placement): Placement, Floorplanning, Partitioning, Hierarchical design [7] Timing, Power, Signal/Power Integrity Analysis and Optimization: Timing analysis, Power analysis, Signal/power integrity, Clock and global signal design [8] Interconnect, Device and Circuit Modeling and Simulation: Interconnect modeling, Interconnect extraction, Package modeling, Circuit simulation, Device modeling/simulation, Library design, Design fabrics, Design for manufacturability, Yield optimization, Reliability analysis, Emerging technologies [9] Test and Design for Testability: Test design, Fault modeling, ATPG, BIST and DFT, Memory, core and system test [10] Analog, RF and Mixed Signal Design and CAD: Analog/RF synthesis, Analog layout, Verification, Simulation techniques, Noise analysis, Analog circuit testing, Mixed-signal design considerations [11] Leading Edge Design Methodology for SOCs and SIPs: Design methodology for Microprocessors, DSP, IP-core, multimedia processors, wireless communication systems, A/D mixed circuits, Memories, Sensors, MEMS chips, FPGAs, Novel reconfigurable systems, Rapid prototyping ASP-DAC 2008 University LSI Design Contest encourages submitting original papers on LSI design and implementation at universities and other educational organizations. Submission of Papers: Deadline for submission: 5 pm KST, July 10 (Tue), 2007 Notification of acceptance: September 28 (Fri), 2007 Deadline for final version: 5 pm KST, November 16 (Fri), 2007 Panels, Special Sessions and Tutorials: Suggestions and proposals are welcome and have to be addressed to the Conference Secretariat (e-mail:aspdac2008@aspdac.com) no later than 5 pm KST, June 8 (Fri.), 2007. Prospective Sponsors: ACM SIGDA, IEEE Circuits and Systems Society, IEEK (The Institute of Electronics Engineers of Korea) ASP-DAC2008 Chairs: General Chair: Chong-Min Kyung (KAIST) Technical Program Co-Chairs: Kiyoung Choi (Seoul National Univ.), Soonhoi Ha (Seoul National Univ.) Technical Program Vice Chair: Ren-Song Tsay (National Tsing Hua Univ.) Conference Secretariat: Please contact Conference Secretariat ( e-mail:aspdac2008@aspdac.com), if you have questions or comments. Specification of the paper submission format will be available at the WEB site: http://www.aspdac.com/aspdac2008/ ============================================================================== Call for Papers ------------------ IEEE Computer Architecture Letters IEEE Computer Architecture Letters seeks submissions from the SIGDA community. CA-Letters is a quarterly forum for fast publication of new, high-quality ideas in the form of short (4-page), critically refereed, technical papers. Decisions are returned within one month of submission. Submissions are accepted on a continuing basis, and accepted letters will be published immediately in the IEEE Digital Library and in the next available print issue. For more details, see: http://www.comp-arch-letters.org For questions, feel free to contact Kevin Skadron (skadron@cs.virginia.edu) or Jean-Luc Gaudiot (gaudiot@uci.edu) ============================================================================== Call For Papers ------------------- Special Issue on Demonstrable Software Systems and Hardware Platforms II We are pleased to announce a call for papers for a second special issue of ACM TODAES on Demonstrable Software Systems and Hardware Platforms. We are interested in research efforts that are dedicated to prototype experimental software systems and/or hardware platforms. Papers should demonstrate how these systems advance the fundamental science of electronic design automation (EDA) and/or offer a significant innovation in their application. Examples of relevant projects might include a system level design tool for improved thermal management, a radiation simulator for testing reconfigurable devices, an optical proximity correction tool for < 65 nm processes, etc. Practical aspects of the software tool or hardware platform development should be accompanied by new and substantive algorithmic and/or theoretic results. Submissions are encouraged from technical papers that describe the works presented at the SIGDA/DAC University Booth in San Diego, 2007. The submission may be based on works that were previously published in refereed conferences such as DAC or ICCAD, however submissions of expanded manuscripts based on the technical papers and Student Design Contest papers at DAC 2007 are especially encouraged. If the submission is an expanded version of a workshop/conference paper, it should contain at least 30% new material, and the authors should state clearly how the submission differs from and/or expands on the workshop/conference paper. Please submit your paper to http://mc.manuscriptcentral.com/acm in the TODAES section. Also, please write .SPECIAL ISSUE ON DEMONSTRABLE SOFTWARE SYSTEMS AND HARDWARE PLATFORMS II. on your cover page and in the notes section of the Web site submission form. We expect a shorter turnaround time for this special issue. About the SIGDA/DAC University Booth: The SIGDA/DAC University Booth provides an opportunity for the university community to demonstrate new EDA tools, design projects, and instructional materials at the Design Automation Conference. The University Booth also provides space for the presentation of EDA vendor literature and programs of interest to the university community. Student participants in the University Booth are typically provided with travel grants to defray the cost of attending the Design Automation Conference. In 2006, the booth had nearly 50 demonstrations from all over the United States, Canada, Brazil, Japan, Korea, France, Singapore, and Taiwan. In honor of our 20th University Booth in 2007 we will have an entirely redesigned booth thanks to sponsorship by Mentor Graphics, Inc. Interested university groups are encouraged to apply via our on-line registration site (http://www.sigda.org/ubooth.html), which typically opens 3 months before Design Automation Conference. Important Dates Submission Deadline: 8/06/07 Acceptance Notice: 2/04/08 Final Manuscript Due: 3/31/08 Guest Editors Alex K. Jones Univ. of Pittsburgh Pittsburgh, PA USA akjones@ece.pitt.edu Robert A. Walker Kent State Univ. Kent, OH USA walker@cs.kent.edu ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ============================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. 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