=============================================================================== SIGDA -- The Resource for EDA Professionals http://www.sigda.org This newsletter is a free service for current SIGDA members and is added automatically with a new SIGDA membersip. Circulation: 2,700 =============================================================================== 1 May 2007 ACM/SIGDA E-NEWSLETTER Vol. 37, No. 9 Online archive: http://www.sigda.org/newsletter =============================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What is Plasmonics? Author: Harry A. Atwater, CalTech From: Igor Markov (3) What is Model-Based Computing? Author: Michael Feldman, HPCwire From: Igor Markov (4) Paper Submission Deadlines From: Hai Zhou (5) Upcoming Conferences and Symposia From: Hai Zhou (6) Upcoming Funding Opportunities From: Qinru Qiu (7) Call for Papers : ASP-DAC 2008 From: Hai Zhou (8) Call for Papers : IEEE Computer Architecture Letters From: Hai Zhou (9) Call For Papers : Special Issue on Demonstrable Software Systems and Hardware Platforms II From: Alex K. Jones =============================================================================== Dear ACM/SIGDA members, This issue's "What is ..." column is linked to the article "The Promise of Plasmonics", by Harry A. Atwater, in Scientific American. The "What is ..." column in the previous newsletter is reprinted. In addition, the "SIGDA News" column contains a number of fresh headlines. We have also updated the contents of other regular columns. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Tony Givargis, E-Newsletter Associate Editor; Matthew Guthaus, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; =============================================================================== SIGDA News ----------------------- "Is IBM Using Nanosoup for Chip Production?" http://news.com.com/8300-10784_3-7-0.html?keyword=IBM+Biology+Nanotechnology Figuring out a way to make semiconductors make themselves would certainly save everyone a lot of time and money, and IBM next week says it will discuss a technique that moves it closer to the goal of self-assembly. On May 3, researchers will provide some details on what IBM says is a commercially practical technique for applying an insulating layer through chips using self-assembly. Now, adding layers and structures to a chip requires costly and time consuming processes: intricate patterns are etched onto microscopic surfaces, sprayed with metals, and then with chemicals to remove excess metal particles. "AMD Fights Back with Boosted Barcelona Performance" http://www.eetimes.com/showArticle.jhtml?articleID=199200545 New test results based on the SPECcpu2006 benchmarks show AMD's Barcelona processor will have "up to a 50 percent advantage in floating point performance and 20 percent in integer performance" over Intel's high-end quad-core chip running "at the same frequency," according to a statement from AMD. "Synplicity Fields ASIC DSP Synthesis" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=199100219 Although Synplicity Inc. left the ASIC synthesis market last year, the company is targeting ASIC designers once again with a new edition of its Synplify DSP product. This time, however, the focus is on electronic system level (ESL) design rather than logic synthesis. "Indian Firm Sets Out to Be 'the TSMC of Design'" http://www.eetimes.com/showArticle.jhtml?articleID=199203885 Rahul Sud, a veteran of the semiconductor industry having worked at Inmos, Lattice Semiconductor and STMicroelectronics, has helped create LogicFab Ltd., an Indian startup company that he would like to see become "the TSMC of design." LogicFab (Delhi) is already working on 90-nm and 65-nm in a design services business model and is profitable said Sud. "Imagine a company with 10,000 design engineers," said Sud making the point that designing chips is not dissimilar to writing software, something engineers do in these sorts of numbers at individual companies across the sub-continent. "NEC, JST and RIKEN Demonstrate World's First Quantum Bit, Qubit, Circuit" http://www.azonano.com/news.asp?newsID=4066 NEC Corporation, Japan Science and Technology Agency (JST) and the Institute of Physical and Chemical Research (RIKEN) have together successfully demonstrated the world's first quantum bit (qubit) circuit that can control the strength of coupling between qubits. Technology achieving control of the coupling strength between qubits is vital to the realization of a practical quantum computer, and has been long awaited in the scientific field. "Nuclear Magnetic Resonance Imaging With 90-nm Resolution" http://www.eetimes.com/showArticle.jhtml?articleID=199200489 Researchers at IBM's Almaden Research Center have found a way to use magnetic resonance imaging (MRI) techniques to see nanoscale objects. Dan Rugar, manager of nanoscale studies at the research center, said the discovery represents "a milestone that has shown that the principles of MRI can be married with scanning microscopy." "Sematech Expands Immersion Funding" http://www.eetimes.com/showArticle.jhtml?articleID=199204084 Sematech and the College of Nanoscale Science and Engineering (CNSE) of the University at Albany will provide additional funding to Columbia University in the area of immersion lithography. The research focuses on the identification and development of novel chemistries to enable double-exposure materials. The work, which will involve testing of materials produced by Columbia, will be conducted at Sematech's Resist Test Center (RTC). "IBM Fills 'Airgap' to Create Faster Chips" http://www.eetimes.com/showArticle.jhtml?articleID=199203454 IBM Corp. scientists have devised a way to create vacuum spaces between copper wires in semiconductors and claimed the technique -- which borrows from nature -- will lead to chips that consume less power and run faster. IBM said Thursday (May 3) its self-assembly nanotechnology process can be incorporated into standard CMOS manufacturing lines without disrupting operations or retooling. Intial results at IBM labs indicate that the electrical signals on chips can flow 35 percent faster, or the chips can consume 15 percent less energy compared to the most advanced chips made using conventional techniques. IBM researchers claim this is the first demonstration of the ability to synthesize mass quantities of self-assembled polymers and integrate them into an existing manufacturing process while achieving improved yields. "New Uses for Small Form-Factor, Low-Power Machines" http://www.acmqueue.com/modules.php?name=Content&pa=showpage&pid=474 These days you have to be more and more creative when tackling home technology projects because the inventory of raw material.second-hand technology.is changing so rapidly. Market and product cycles continue to shrink, standard form factors are being discarded to drive down costs, and pricing is becoming more dependent on market value and less on direct manufacturing cost. "Design-for-Manufacturing Mantra: Simplify, Simplify" http://www.eetimes.com/showArticle.jhtml?articleID=199200261 Current approaches to design-for-manufacturability (DFM) may be yielding too little for the amount of effort and cost involved, according to IC design experts at the recent IEEE Electronic Design Process (EDP) workshop. Rather than throw complicated analysis tools at designers, speakers said, DFM is best addressed through design rules, preverified blocks and improved standard-cell libraries. "818 Engineers Describe Verification Tool Use" http://www.eetimes.com/showArticle.jhtml?articleID=199201139 Engineers are increasingly shunning specialized verification languages, are continuing to embrace Verilog, and are shifting slightly towards Synopsys and away from Cadence Design Systems in simulation, according to a new "verification census" survey of 818 engineers. The survey was conducted by John Cooley, moderator of the E-Mail Synopsys Users Group (ESNUG). The verification survey also shed new light on two startups. One is "functional qualification" startup Certess, which came into public view in March but did not announce a product. Another is stealth-mode startup Nusym, which has made no announcements. "IBM, Intel, Microsoft Tout Technology Future" http://www.eetimes.com/showArticle.jhtml?articleID=199201735 A glimpse into the future of computing technology, provided by researchers from IBM, Intel, and Microsoft, reveals photo-realistic virtual words rendered on the fly, desktop file manipulation using hand gestures, and presence information relayed by ubiquitous sensors. At the Gartner IT/xpo, Jerry Battista, director of technology management for Intel; Eric Horvitz, principal researcher for Microsoft Research; and Paul Bloom, IBM's research executive for communications industries, fielded questions on stage from two Gartner VPs about future technology. "Sun and I.B.M. to Offer New Class of High-End Servers" http://www.nytimes.com/2007/04/26/technology/26compute.html?_r=1&oref=slogin Sun Microsystems and IBM both introduced new high-end server systems that provide an early glimpse into a new era of computing. Sun's machine, designed by the company co-founder Andreas Bechtolsheim, is an ultra-fast video server potentially powerful enough to send different standard video streams simultaneously to everyone watching television in a city the size of New York. IBM's machine is a video game server that blends a mainframe computer with the company's Cell microprocessors, creating a system that could support thousands of users interacting in a three-dimensional simulated on-screen world, described as the "metaverse." Both machines will cost hundreds of thousands or even millions of dollars, but they represent that the modern computing world is moving away from the era of cheap microprocessors that started two decades ago. Former ACM President David Patterson, a computer scientist at the University of California, Berkeley, said he believes that is still more to be done with combining microprocessors, but "if the future of computing is the data center and the consumer gadget," the two new machines could be the wave of the future. "It's a new era--it's the era of application-specific computing," said Bernard S. Meyerson, chief technologist of IBM's Systems and Technology Group. Meyerson said that IBM has introduced hybrid computing, and that computers will now be custom-designed for specific purposes. "EE Times: Outgoing Sony Exec Kutaragi Already Planning PS4" http://www.eetimes.com/showArticle.jhtml?articleID=199202196 Playstation inventor Ken Kutaragi, who will retire as chairman and group CEO of Sony Computer Entertainment Inc. on June 19, is already thinking ahead to Playstation 4 and beyond. In an exclusive interview with EE Times, Kutaragi said: "As a matter of course, I have the vision of Playstation 4, 5 and 6, which will merge into the network." "Research at Sun Labs" http://www.eetimes.com/showArticle.jhtml?articleID=199202121 Sun Microsystems put the spotlight on its next-generation technology and showed off research projects that ranged from faster switches and more efficient servers to 3-D virtual workplaces in an open house for analysts and reporters. The computer maker on Thursday held its annual Sun Labs open house and brought out the researchers and scientists responsible for developing the innovative products the company needs to survive in a commodity market. Robert Sproull, director of Sun Labs, made clear that Sun has big ambitions. "General purpose computers have to be rethought." In a meeting last month with reporters, Sun CEO Jonathan Schwartz said, "R&D is key when you make money from a commodity. You need to spend enormous amounts of money to differentiate." "XO Laptop: Child's Play" http://www.pcworld.com/article/id,131330-c,thinandlightnotebooks/article.html One Laptop Per Child product deemed basic but useful, as initiative to spread affordable technology. "Mouse Brain Simulated on BlueGene" http://news.bbc.co.uk/2/hi/technology/6600965.stm Researchers from IBM's Almaden Research Lab and University of Nevada ran a "cortical simulator" that was as big and as complex as half of a mouse brain on the BlueGene L supercomputer. Half a real mouse brain is thought to have about eight million neurons each with up to 8,000 synapses. "Object-Oriented Modeling with UML: A Study of Developers' Perceptions" http://www.acmqueue.com/modules.php?name=Content&pa=showpage&pid=468 The object-oriented (OO) approach provides a powerful and effective environment for modeling and building complex systems. It supports a variety of techniques for analyzing, designing, and implementing flexible and robust real-world systems, providing benefits such as encapsulation, polymorphism, inheritance, and reusability "Security Is Harder Than You Think" http://www.acmqueue.com/modules.php?name=Content&pa=showpage&pid=174 Many developers see buffer overflows as the biggest security threat to software and believe that there is a simple two-step process to secure software: switch from C or C++ to Java, then start using SSL (Secure Sockets Layer) to protect data communications. It turns out that this nave tactic isn't sufficient. In this article, we explore why software security is harder than people expect, focusing on the example of SSL. "Peer Code Reviews: Two Heads Are Better Than One" http://www.embedded.com/shared/printableArticle.jhtml?articleID=199204097 Over a 10 month period at Cisco Systems, 50 developers performed 2500 reviews on 3.2 million lines of code. This was on production code in the LiveMeeting project, not an academic setting. Developers were in San Jose, Boulder, Hyderabad, and Budapest. "What's different about multiprocessor software" http://www.embedded.com/showArticle.jhtml?articleID=198701641 While real-time operating systems provide apparent concurrency on a single processor, multiprocessor platforms provide true concurrency. The concurrency and performance provided by multiprocessors can be very powerful but also harder to analyze and debug. "A Methodology for Front-End Power Predictability" http://www.edn.com/article/CA6434905.html ower closure has moved to the forefront of design challenges for today's chip projects. Leakage power increases with each new process generation. Smaller geometries enable more functionality to be fit into a smaller space, running at a higher speed. This creates exponential growth in power density, presenting a heat removal challenge for all types of design, especially high-speed applications that have never had to worry about power before. "Qualcomm Signs to Use Arithmatica's Mathematics" http://www.eetimes.com/news/design/showArticle.jhtml?articleID=199200555 Arithmatica Inc., a company that offers to improve its customers' integrated circuits by offering innovations in mathematical circuit blocks, has added Qualcomm Inc. (San Diego, Calif.) to its list of customers. "Squeezing a Low-Cost Multiprocessor Platform Out of 130 nm" http://www.edn.com/article/CA6434359.html Sometimes designing an SOC (system on chip) on the latest and greatest process technology is not what it takes to make an impact on the cost-conscious consumer-electronics market. That a lesson LSI Logic engineers took to heart in designing LSI Zevio 1020 multimedia-application-processor platform. "Commentary: ESL Should Drive Emulation" http://www.eetimes.com/news/design/showArticle.jhtml?articleID=199000904 Conventional wisdom says that when it comes to design, you can either have a design that simulates quickly, but is not accurate. Or, you can have one that is hardware accurate but runs far too slowly for meaningful software debug or architectural performance analysis. ============================================================================== What is Plasmonics? -------------------------------- Harry A. Atwater, CalTech http://www.sciam.com/article.cfm?chanID=sa006&articleID=5BED2E76-E7F2-99DF-3A1C740338CE5666&ref=rss ============================================================================== What is Model-Based Computing? --------------------------------- Michael Feldman, HPCwire http://www.hpcwire.com/hpc/1321157.html ============================================================================== Submission deadlines: --------------------- HiPC'07 - Int'l Conference on High Performance Computing Goa, India Dec 18-21, 2007 Deadline: May 7, 2007 http://www.hipc.org/ EUC'07 - Int'l Conference on Embedded and Ubiquitous Computing Taipei, Taiwan Dec 17-20, 2007 Deadline: May 17, 2007 http://csie.ntu.edu.tw/~euc07/ ICPADS'07 - Int'l Conference on Parallel and Distributed Systems Hsinchu, Taiwan Dec 5-7, 2007 Deadline: May 20, 2007 http://www.ccrc.nthu.edu.tw/icpads2007/ MICRO'07 - Int'l Symposium on Microarchitecture Chicago, IL Dec 1-5, 2007 Deadline: Jun 1, 2007 http://www.microarch.org/micro40/ HiPEAC'08: Int'l Conference on High Performance Embedded Architectures & Compilers Goteborg, Sweden Jan 27-29, 2008 Deadline: Jun 10, 2007 http://www.hipeac.net/hipeac2007/ ICM'07 - Int'l Conference on Microelectronics Cairo, Egypt Dec 29-31, 2007 Deadline: Jun 15, 2007 http://www.ieee-icm.com/ PDCS'07 - Int'l Conference on Parallel and Distributed Computing Systems Cambridge, MA Nov. 19-21, 2007 Deadline: Jun 15, 2007 http://www.iasted.org/conferences/home-590.html ICFPT'07 - Int'l Conference on Field-Programmable Technology Kitakyushu, Japan Dec 12-14, 2007 Deadline: Jun 25, 2007 http://www.kameyama.ecei.tohoku.ac.jp/icfpt07/ ASP-DAC'08 - Asia and South Pacific Design Automation Conference (sponsored by SIGDA) Seoul, Korea Jan 21-24, 2008 Deadline: Jul 10, 2007 http://www.aspdac.com/aspdac2008/ VLSI'08 - Int'l Conference on VLSI Design (sponsored by SIGDA) ES'08 - Int'l Conference on Embedded Systems Hyderabad, India Jan 4-8, 2008 Deadline: Jul 10, 2007 http://vlsiconference.com/vlsi2008/ ============================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 http://www.nocsymposium.org/ ISVLSI'07 - Annual Symposium on VLSI Porto Allegre, Brazil May 9-11, 2007 http://www.inf.ufrgs.br/isvlsi2007/ RSP'07 - Int'l Workshop on Rapid System Prototyping Porto Alegre, Brazil May 28-30, 2007 http://www.rsp-workshop.org/ IESS'07 - Int'l Embedded Systems Symposium Irvine, CA May 29-Jun 1, 2007 http://www.iess.org/ ICICDT'07 - Int'l Conference on IC Design & Technology Austin, TX May 30-Jun 1, 2007 http://www.icicdt.org/ MEMOCODE'07 - Int'l Conference on Formal Methods and Models for Codesign (sponsored by SIGDA) Nice, France May 30-Jun 1, 2007 http://memocode.irisa.fr/ IWLS'07 - Int'l Workshop on Logic & Synthesis (sponsored by SIGDA) San Diego, CA May 30-Jun 1, 2007 http://www.iwls.org/ MSE'07 - Int'l Conference on Microelectronic Systems Education San Diego, CA Jun 3-4, 2007 http://www.mseconference.org/ DAC'07 - Design Automation Conference (sponsored by SIGDA) San Diego, CA Jun 4-8, 2007 http://www.dac.com/ CAV'07 - Int'l Conference on Computer Aided Verification Berlin, Germany Jul 3-7, 2007 http://www.cav2007.org/ ASAP'07 - Int'l Conference on Application-specific Systems, Architectures and Processors Montreal, Canada July 9-11, 2007 http://asap-conference.org/ ACSD'07 - Int'l Conference on Application of Concurrency to System Design (Sponsored by SIGDA) Bratislava, Slovak Republic Jul 10-13 2007 http://www.acsd.sk/ MWSCAS/NEWCAS'07 - Int'l Midwest Symposium on Circuits and Systems/ Int'l NEWCAS Conference Montreal, Canada Aug 5-8, 2007 http://newcas.grm.polymtl.ca/ FPL'07 - Int'l Conference on Field-Programmable Logic and Applications Amsterdam, Holland Aug 27-29, 2007 http://www.fpl.uni-kl.de/fpl/ DSD'07 - Euromicro Conference on Digital System Design Lubeck, Germany Aug 29-31, 2007 http://www.dsdconf.org/ PATMOS'07 - Power and Timing Modeling, Opt. & Sim. Goteborg, Sweden Sep 3-5, 2007 http://www.ce.chalmers.se/research/conference/patmos07/ SBCCI'07 - Symposium on Integrated and Systems Design (sponsored by SIGDA) Rio de Janeiro, Brazil Sep 3-6, 2007 http://www.sbcci.pads.ufrj.br/sbcci/index_sbcci.html PACT'07 - Int'l Conference on Parallel Architectures and Compilation Techniques Brasov, Romania Sep 15-19, 2007 http://www.pactconf.org/ CICC'07 - Custom Integrated Circuits Conference San Jose, CA Sep 16-19, 2007 http://www.ieee-cicc.org/ CODES+ISSS'07 - Int'l Conference on Hardware-Software Codesign and System Synthesis (sponsored by SIGDA) Salzburg, Austria sep 30-Oct 5, 2007 http://www.codes-isss.org/ VLSI-SoC'07 - Int'l Conference on Very Large Scale Integration Atlanta, GA Oct 15-17, 2007 http://www.vlsisoc2007.gatech.edu/ ICCAD'07 - Int'l Conference on Computer-Aided Design (sponsored by SIGDA) San Jose, CA Nov 4-8, 2007 http://www.iccad.com/ ============================================================================== Upcoming Funding Opportunities -------------------------------- ACM Doctoral Dissertation Award Deadline: August 31, 2007 http://fundingopps.cos.com/alerts/33218?id=33218&if=alert NIH NLM Knowledge Management & Applied Informatics Grants Deadline: May 25, 2007 September 25, 2007 January 25, 2008 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-236.html Continued Development and Maintenance of Software (R01) Deadline: May 17, 2007 September 13, 2007 http://grants1.nih.gov/grants/guide/pa-files/PAR-07-235.html NASA Applied Information Systems Research - NNH07ZDA001N-AISR Deadline: To be announced (TBA) http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId=%7B89FBF877-DD5F-AC6E-DAB3-AE19504EA70D%7D&path=open DOD Cognitive Technology Threat Warning System (CT2WS) Deadline: April 11, 2008 http://fedbizopps.cos.com/cgi-bin/getRec?id=20070412a1 Warrior Systems Technologies - Body-Worn Systems, Hand Held Devices, and Smart-Lightweight Electronic Components/Modules for Soldier Protection, Knowledge Management and Cognitive Improvement Deadline: Continuous. (April 1, 2007 ~ March 31, 2009) https://www3.natick.army.mil/ssbaa.htm Homeland Security (2.2.1) - N61339-02-R-0071 Deadline: Continuous. This BAA expires on January 30, 2008 http://www1.fbo.gov/spg/DON/NAVAIR/N61339/N61339-02-R-0071/Attachments.html Microsystems Technology Office-Wide Deadline: January 14, 2009 http://www.fbo.gov/spg/ODA/DARPA/CMO/BAA07-18/Attachments.html SPINS in Semiconductors Deadline: December 31, 2008 http://fundingopps.cos.com/alerts/57993 Artificial Intelligence Technologies Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/baa.htm Quantum Information Science and Technology Deadline: December 31, 2008 http://heron.nrl.navy.mil/contracts/0708baa/baa.htm Young Investigator Program (YIP) January 12, 2008 http://www.onr.navy.mil/sci_tech/3t/corporate/yip.asp High Density Optical Memory Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Quantum Electronic Solids Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Distributed Intelligence Deadline: Continuous http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF Accelerating Discovery in Science and Engineering Through Petascale Simulations and Analysis (PetaApps) - NSF 07-559 Deadline: July 23, 2007 http://www.nsf.gov/pubs/2007/nsf07559/nsf07559.htm Biological Databases and Informatics - NSF 05-577 Deadline: July 9, 2007 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=5444 DARPA Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm Sloan Foundation Sloan Research Fellowships Deadline: September 15, 2007 http://www.sloan.org/programs/scitech_fellowships.shtml ============================================================================== Call for Papers ----------------- ASP-DAC 2008 Asia and South Pacific Design Automation Conference 2008 http://www.aspdac.com/aspdac2008/ January 21-24, 2008 COEX, Seoul, Korea Aims of the Conference: ASP-DAC 2008 is the thirteenth in a series of annual international conferences on VLSI design automation. Asia and South Pacific region is one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances in the technologies related to Electronic Design Automation (EDA) and discussing the future directions. The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. A wide variety of those scientists, engineers, and students who are interested in theoretical issues in EDA are also welcome. Areas of Interest: Original papers on, but not limited to, the following areas are invited. [1] System Level Design: System VLSI and SOC design methods, System specification, Specification languages, Design languages, Hardware-software co-design, Co-simulation, Co-verification, Platform-based design, Design reuse and IP's [2] Embedded and Real-Time Systems: Low power system design, Network on chip, Communication architecture, Memory architecture, Real-time OS and middleware, Compilation techniques, ASIP synthesis [3] Behavioral/Logic Synthesis and Optimization: Behavioral/RTL synthesis, Technology-independent optimization, Technology mapping, Interaction between logic design and layout, Sequential and asynchronous logic synthesis [4] Validation and Verification for Behavioral/Logic Design: Logic simulation, Symbolic simulation, Formal verification, Equivalence checking, Transaction-level/RTL and gate-level modeling and validation [5] Physical Design (Routing): Routing, Repeater issues, Interconnect optimization, Interconnect planning, Module generation, Layout verification [6] Physical Design (Placement): Placement, Floorplanning, Partitioning, Hierarchical design [7] Timing, Power, Signal/Power Integrity Analysis and Optimization: Timing analysis, Power analysis, Signal/power integrity, Clock and global signal design [8] Interconnect, Device and Circuit Modeling and Simulation: Interconnect modeling, Interconnect extraction, Package modeling, Circuit simulation, Device modeling/simulation, Library design, Design fabrics, Design for manufacturability, Yield optimization, Reliability analysis, Emerging technologies [9] Test and Design for Testability: Test design, Fault modeling, ATPG, BIST and DFT, Memory, core and system test [10] Analog, RF and Mixed Signal Design and CAD: Analog/RF synthesis, Analog layout, Verification, Simulation techniques, Noise analysis, Analog circuit testing, Mixed-signal design considerations [11] Leading Edge Design Methodology for SOCs and SIPs: Design methodology for Microprocessors, DSP, IP-core, multimedia processors, wireless communication systems, A/D mixed circuits, Memories, Sensors, MEMS chips, FPGAs, Novel reconfigurable systems, Rapid prototyping ASP-DAC 2008 University LSI Design Contest encourages submitting original papers on LSI design and implementation at universities and other educational organizations. Submission of Papers: Deadline for submission: 5 pm KST, July 10 (Tue), 2007 Notification of acceptance: September 28 (Fri), 2007 Deadline for final version: 5 pm KST, November 16 (Fri), 2007 Panels, Special Sessions and Tutorials: Suggestions and proposals are welcome and have to be addressed to the Conference Secretariat (e-mail:aspdac2008@aspdac.com) no later than 5 pm KST, June 8 (Fri.), 2007. Prospective Sponsors: ACM SIGDA, IEEE Circuits and Systems Society, IEEK (The Institute of Electronics Engineers of Korea) ASP-DAC2008 Chairs: General Chair: Chong-Min Kyung (KAIST) Technical Program Co-Chairs: Kiyoung Choi (Seoul National Univ.), Soonhoi Ha (Seoul National Univ.) Technical Program Vice Chair: Ren-Song Tsay (National Tsing Hua Univ.) Conference Secretariat: Please contact Conference Secretariat ( e-mail:aspdac2008@aspdac.com), if you have questions or comments. Specification of the paper submission format will be available at the WEB site: http://www.aspdac.com/aspdac2008/ ============================================================================== Call for Papers ------------------ IEEE Computer Architecture Letters IEEE Computer Architecture Letters seeks submissions from the SIGDA community. CA-Letters is a quarterly forum for fast publication of new, high-quality ideas in the form of short (4-page), critically refereed, technical papers. Decisions are returned within one month of submission. Submissions are accepted on a continuing basis, and accepted letters will be published immediately in the IEEE Digital Library and in the next available print issue. For more details, see: http://www.comp-arch-letters.org For questions, feel free to contact Kevin Skadron (skadron@cs.virginia.edu) or Jean-Luc Gaudiot (gaudiot@uci.edu) ============================================================================== Call For Papers ------------------- Special Issue on Demonstrable Software Systems and Hardware Platforms II We are pleased to announce a call for papers for a second special issue of ACM TODAES on Demonstrable Software Systems and Hardware Platforms. We are interested in research efforts that are dedicated to prototype experimental software systems and/or hardware platforms. Papers should demonstrate how these systems advance the fundamental science of electronic design automation (EDA) and/or offer a significant innovation in their application. Examples of relevant projects might include a system level design tool for improved thermal management, a radiation simulator for testing reconfigurable devices, an optical proximity correction tool for < 65 nm processes, etc. Practical aspects of the software tool or hardware platform development should be accompanied by new and substantive algorithmic and/or theoretic results. Submissions are encouraged from technical papers that describe the works presented at the SIGDA/DAC University Booth in San Diego, 2007. The submission may be based on works that were previously published in refereed conferences such as DAC or ICCAD, however submissions of expanded manuscripts based on the technical papers and Student Design Contest papers at DAC 2007 are especially encouraged. If the submission is an expanded version of a workshop/conference paper, it should contain at least 30% new material, and the authors should state clearly how the submission differs from and/or expands on the workshop/conference paper. Please submit your paper to http://mc.manuscriptcentral.com/acm in the TODAES section. Also, please write .SPECIAL ISSUE ON DEMONSTRABLE SOFTWARE SYSTEMS AND HARDWARE PLATFORMS II. on your cover page and in the notes section of the Web site submission form. We expect a shorter turnaround time for this special issue. About the SIGDA/DAC University Booth: The SIGDA/DAC University Booth provides an opportunity for the university community to demonstrate new EDA tools, design projects, and instructional materials at the Design Automation Conference. The University Booth also provides space for the presentation of EDA vendor literature and programs of interest to the university community. Student participants in the University Booth are typically provided with travel grants to defray the cost of attending the Design Automation Conference. In 2006, the booth had nearly 50 demonstrations from all over the United States, Canada, Brazil, Japan, Korea, France, Singapore, and Taiwan. In honor of our 20th University Booth in 2007 we will have an entirely redesigned booth thanks to sponsorship by Mentor Graphics, Inc. Interested university groups are encouraged to apply via our on-line registration site (http://www.sigda.org/ubooth.html), which typically opens 3 months before Design Automation Conference. Important Dates Submission Deadline: 8/06/07 Acceptance Notice: 2/04/08 Final Manuscript Due: 3/31/08 Guest Editors Alex K. Jones Univ. of Pittsburgh Pittsburgh, PA USA akjones@ece.pitt.edu Robert A. Walker Kent State Univ. Kent, OH USA walker@cs.kent.edu ============================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ============================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. 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