======================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org ======================================================================== 1 September 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 17 Online archive: http://www.sigda.org/newsletter ======================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What are Elastic Circuits? Contributing author: Jordi Cortadella, Universitat Politecnica de Catalunya Contributing author: Mike Kishinevsky, Intel Corporation Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Upcoming Funding Opportunities Qinru Qiu (6) Call For Papers - ACM GLSVLSI 2007 Hai Zhou (7) Call For Papers - SELSE-3 Workshop Cristian Constantinescu (8) FOUNDATIONS AND TRENDS IN ELECTRONIC DESIGN AUTOMATION James Finlay (9) 5th SIGDA CADathlon at ICCAD 2006 Geert Janssen (10) *EXTENDED* Advance Registration Deadline for *ISLPED 2006* 2006 International Symposium on Low Power Electronics and Design Diana Marculescu ======================================================================== Dear ACM/SIGDA members, As the summer cools down, the SIGDA newsletter will be picking up pace. In addition to SIGDA news, this issue covers a number of conference submission deadlines in the Fall, as well as a call for participation in the CADathlon competition at ICCAD, and a calls for papers for GLSVLSI, ILPED and SELSE-3. We are resuming the "What is ...?" column after a summer break with an entry covering elastic circuits, and plan to continue the column on a monthly basis. As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; ======================================================================== SIGDA News ----------------------- "The DAC Trivia Contest Winners" The DAC Trivia contest included in the SIGDA flyer distributed at DAC 2006 has three winners! Please join us in congratulating them for their DAC Trivia Knowledge: * Don Thomas, Carnegie Mellon University - special congratulations for getting seven names right * Igor Markov, University of Michigan and Charlie Rosenthal - each got one of the names right Winners will receive free 2007 SIGDA membership which provides access to all SIGDA conference/symposia proceedings available in the ACM Digital Library at http://www.acm.org/dl from inception until present. To find the correct answers, check the picture on page 7 (printed as page 24) of the SIGDA Newsletter, volume 8, issue 3, Dec. 1978 available in the ACM DL at: http://portal.acm.org/ft_gateway.cfm?id=382658&type=pdf&coll=portal&dl=ACM&CFID=930261 Intel is Expecting to Lay off 10% of Their Workforce http://slashdot.org/articles/06/09/01/132252.shtml The Santa Clara, Calif.-based chipmaker, having suffered several financially disappointing quarters, launched an internal analysis in April to find ways to increase its efficiency. The CEO, Paul Otellini, is scheduled to announce the results of the analysis, including the layoff, on Tuesday after the stock market closes, sources familiar with the plans said. Intel has about 100,000 employees worldwide, so the cut could be as high as 10 percent of the company's staff. "How Biotech Is Driving Computing" http://money.cnn.com/2006/08/18/technology/futureboy0818.biz2/ What are the toughest computations that keep fastest supercomputers busy? Apparently, the answer is "biomolecular simulations", including the analysis of DNA and proteins. IBM is selling time on Blue Gene to QuantumBio, a company that offers protein-testing services to pharmaceutical companies. Japan's MDGrape-3 computer that broke the PetaFlop/s barrier last month was designed and optimized for such applications --- it cannot even run the standard Linpack benchmarks required to place in the Supercomputing 500 list. "The Future of Microprocessors" http://www.acmqueue.com/modules.php?name=Content&pa=showpage&pid=326 The performance of microprocessors that power modern computers has continued to increase exponentially over the years for two main reasons. Along these lines, chip multiprocessors' promise of huge performance gains is now a reality. "In Single-Molecule Electronic Devices, Flatter Molecules Conduct Electricity Better" http://www.azonano.com/news.asp?newsID=2925 Columbia research scientist Latha Venkataraman has demonstrated that in creating single-molecule electronic devices, flatter molecules conduct electricity better. That principle has long been suspected, but to demonstrate it definitively required an innovation to existing methods for measuring conductance in nano-scale objects. "Nanobattery Technology Could Eliminate Fire Risks" http://www.eetimes.com/showArticle.jhtml?articleID=192203318 Scientists at Tel Aviv University have developed and patented a nanobattery technology for fast charge/discharge batteries that they claim could provide an alternative source of power for mobile devices while eliminating fire hazards associated with current lithium-based batteries. The device includes about 30,000 miniature batteries on an area as small as 1 cm2 connected in parallel. This architecture is said to provide high electrical power output without the risk of overheating, a major cause of flammability in laptop computer and other mobile batteries. "Putting a New Spin on Quantum Dots" http://www.newscientisttech.com/article/dn9768-electronspin-trick-boosts-quantum-computing.html Quantum dots have been primarily studied for their switching speed, which is projected in the TeraHertz range. However, new research shows that quantum dots allow working not only with conventional 0s and 1s, but also with quantum bits (or qubits). The breakthrough experiment described in the Nature journal (vol.442, p.766) by a team led by Lieven Vandersypen at Delft University of Technology shows how to manipulate electron spins stored in quantum dots. A major benefit of this qubit technology is the use of existing GaAs chip lithography. Quantum dots are 100nm across and may allow building large quantum computers. "Intel CTO: Multicore Performance Standards Needed" http://www.eetimes.com/showArticle.jhtml?articleID=192204967 The accelerating transition to multicore processors poses the next major challenge to systems developers, according to Justin Rattner, an Intel senior fellow and chief technology officer. In a keynote presentation at this week's IEEE Hot Chips Conference at Stanford University, Rattner noted that designers must deal with complex memory hierarchies and sophisticated on-chip interconnect fabrics to ensure the cores are not data starved. At the same time, the processor must provide explicit thread support and deal with time-critical functions, as well as include fixed-function accelerators. "EDA Poised To Grow Faster Than IC Market, Analyst Says" http://www.eetimes.com/showArticle.jhtml?articleID=192205057 The increase in IC design cost and the size of design teams at the 65-nanometer node presents an opportunity for EDA, which can increase its growth rate if it can provide more productive solutions that enable customers to do 65-nm designs without the need to continually increase headcount, according to Handel Jones, CEO of International Business Strategies Inc. Jones believes the EDA market is poised to outgrow the IC industry. In 1996, he said, R&D expenditures for semiconductor companies were roughly 5.5 percent of revenues. By 2010, he said, product R&D will be almost 14 percent of revenue, with some companies spending as much as 20 to 25 percent. "Companies can't keep increasing R&D," Jones said. "They have got to make engineers more productive. The way you do that is increasing the tool productivity." "Quantum Cryptographic Data Network Demonstrated" http://www.sciencedaily.com/releases/2006/08/060828211555.htm A joint collaboration between Northwestern University and BBN Technologies of Cambridge, Mass., has led to the first demonstration of a truly quantum cryptographic data network. By integrating quantum noise protected data encryption with Quantum Key Distribution (QKD), the researchers have developed a complete data communication system with extraordinary resilience to eavesdropping. BBN has built and demonstrated the world's first quantum network with untrusted network switches, delivering end-to-end key distribution via high-speed 24/7 QKD since 2004. The combined QKD/AlphaEta system has been demonstrated in a nine kilometer link between BBN headquarters and Harvard University in Cambridge, Mass. The AlphaEta encrypted signal carried OC-3 (155Mb/s) SONET data between the two nodes. A fresh encryption key of about 1 kilobit was repetitively loaded every three seconds. In a separate test, the AlphaEta encrypted signal was looped back multiple times to create an effective 36 kilometer link where more than 300 consecutive key exchanges were demonstrated. "Software and the Concurrency Revolution" http://www.acmqueue.com/modules.php?name=Content&pa=showpage&pid=332 Concurrency has long been touted as the next big thing but for the past 30 years, mainstream software development has been able to ignore it. Our parallel future has finally arrived: new machines will be parallel machines, and this will require major changes in the way we develop software. "The Evolving Semiconductor Infrastructure vs. The Inconvenient Truth" http://www.chipdesignmag.com/chipdesigner/july2006.html#Section_1 By now, most people have heard of Al Gore's movie on global warming and the impending crisis it represents for our planet. That is a crisis if there ever was one, and Gore's clear attempt to raise awareness is timely and remarkable in its message's effectiveness. "Cool Asynchronous Designs Emerge at Hot Chips" http://www.edn.com/index.asp?layout=articlePrint&articleID=CA6364999 Asynchronous-logic design has a complex recent history. For a number of years, it has been obvious that many blocks would benefit from a self-timed design that eliminated the clocks that form the skeleton of modern synthesis-based logic methodology. But unfamiliarity, lack of libraries and tools, and, frankly, the extreme inertia of many logic designers have kept this promising realm nearly unexplored. "Tutorial: On-chip MCU debug and the end of the (off-chip) ICE Age" http://www.embedded.com/shared/printableArticle.jhtml?articleID=192300011 In the age of non-volatile memory-based MCUs and devices, one very useful role of on-chip debug is in support of Flash memory based software routines. These modern Flash memories typically include an on-chip state machine that automates most of the steps needed to erase pages of Flash or program Flash locations. "Jasper Offers Free Verification Planning Tool" http://www.eetimes.com/showArticle.jhtml?articleID=192500570 Jasper Design Automation is making available a free tool for tracking the progress of verification plans. According to Jasper, the GamePlan Verification Planner is a "first-of-its-kind tool" that promotes ollaboration between verification team members through a single environment that dentifies the design features that need to be tested and the verification technologies required for testing. GamePlan Verification Planner provides a solution for systematic verification, enabling vital prioritization and progress tracking for each feature tested, according to the company. Jasper has created an online micro-site for GamePlan at http://www.jasper-da.com/gameplan/ offering free downloads of software and documentation, access to user forums and areas for sharing ideas and verification test plan examples. "How Much PC Memory is Enough?" http://www.eetimes.com/showArticle.jhtml?articleID=192500714 Bill O'Brien benchmarks the impact of larger memory on PC performance, going from 512MB to 2GB in single- and dual-channel configurations. ======================================================================== What are Elastic Circuits ? --------------------------------- Jordi Cortadella, Universitat Politecnica de Catalunya, Barcelona, Spain Mike Kishinevsky, Intel Corporation, Hillsboro, OR USA ------------------------------------------------------------------------- When designing or analyzing a digital synchronous circuit, one implicitly assumes the existence of a clock that determines the frequency at which computations are performed and input/output data are transferred. In contrast, this assumption does not apply to software programs, for which one assumes that the response time will depend on a variety of factors beyond the control of the user: the current workload of the operating system, the cache hit ratio, the traffic on the network, etc. One could say that software programs are elastic, since they can adapt themselves to the specific characteristics of the resources required to execute them and to the environment that interacts with them. With current nanotechnologies, circuits resemble more a distributed network of devices with variable computation and communication delays. For example, a factor like the temperature of a specific region of a chip may change the frequency of a local clock and the response time of a particular functional unit. However, conventional circuits are often not designed in a way that allows changing the timing behavior of some components arbitrarily without modifying the functional behavior of the system. For several decades researchers have studied systems that are tolerant to the variability of different parameters of a circuit: delay, power supply, temperature. Typically such research implies the assumption that the behavior of the systems cannot entirely depend on a global clock that forces every component to work and deliver data at a fixed frequency. The natural way of improving the tolerance to variability of parameters is to eliminate the clock from the system, making the entire system asynchronous. Like a distributed network, the components of an asynchronous circuit talk to each other by means of handshake signals that commit to some protocol. Typically, there is a local bi-directional synchronization for each pair of components that must exchange data. In its minimal form, the synchronization is implemented by a pair of signals called request and acknowledge. The term "elastic circuit" initially referred to pipelines that were tolerant to the variability of input data arrival and computation delays. For example, Ivan Sutherland invoked elasticity in his Turing award lecture when he discussed micropipelines ---- a structure that allows one to build pipelined systems in a hierarchical and composable way. Asynchronous systems imply additional design complexity, since they often encode information in signal transitions. Therefore, the asynchronous circuit must not produce spurious signal transitions that could result in misinterpretations of the information. It is important to entirely avoid spurious transitions (also called glitches) or to restrict glitches to the timing intervals during which the signal is not observed. Both constraints makes the design of asynchronous circuits considerably more challenging. For this reason, several research efforts limit the elasticity of asynchronous systems to discrete multiples of a certain time interval, e.g., the period of a synchronous clock. Since the mid-90's, this idea has evolved and reappeared in different forms under several names, such as synchronous emulation of asynchronous circuits, synchronous handshake circuits, latency-insensitive design or synchronous elastic systems. In all these variants, the systems are still event-driven, but events are synchronized to a common clock. At a first sight, a synchronous elastic system resembles a conventional clock circuit, but every data item in it has an associated valid bit. Every functional unit can also issue a stop bit to stall the activity of the neighboring units when it is not ready to receive information. Conceptually, these bits play the same role as the request/acknowledge wires in asynchronous systems. By incorporating synchronicity, the design of elastic systems becomes easier. As in regular synchronous circuits, signals must stabilize only by the end of the clock period and are allowed to have glitches. Therefore, the existing infrastructure and methods for synchronous design can be re-used for synchronous elastic circuits. Elastic circuits pose new opportunites and challenges in the design of future digital systems. Their tolerance to variable latency motivates the design of functional units optimized for the most frequent cases (instead of the worst case), offering a better average delay and new design trade-offs. They enable dynamic changes in latencies (in a synchronous case) or delays (in the asynchronous case) and dynamic adaptation to different environmental scenarios (temperature, power supply, clock frequency, etc). Layout synthesis can benefit from elasticity, since elasticity can be introduced into layout with few incremental changes enabling fine-tuning of the system for better power and performance. Elasticity introduces a certain degree of timing non-determinism making the optimal scheduling a more challenging problem. It also allows for new dimensions in high-level optimization and transformations. References: ----------- I.E. Sutherland, Micropipelines, Commun. ACM, 32(6): 720-738, June 1989. R. Manohar and A.J. Martin, Slack Elasticity in Concurrent Computing, Lecture Notes In Computer Science, Vol. 1422, Proceedings of the Mathematics of Program Construction Pages: 272 - 285, 1998, ISBN 3-540-64591-8 L. Carloni, K. McMillan, and A. Sangiovanni-Vincentelli, Theory of latency-insensitive design, IEEE Trans. on CAD, 20(9):1059-1076, Sep. 2001. J. Sparsų and S. Furber (Eds.), Principles of Asynchronous Circuit Design: A Systems Perspective, Springer, 2002, ISBN 0-7923-7613-7 H. M. Jacobson, P. N. Kudva, P. Bose, P. W. Cook, S. E. Schuster, E. G. Mercer, and C. J. Myers, Synchronous interlocked pipelines, In Proc. Int. Symp. on Adv. Res. in Asynchronous Circuits and Systems, pp. 3­12, 2002. J. Cortadella, M. Kishinevsky, and B. Grundmann, Synthesis of synchronous elastic architectures, In Proc. ACM/IEEE Design Automation Conference, pp. 657-662, July 2006. ======================================================================== Submission deadlines: --------------------- DATE'07 - Design Automation and Test in Europe Nice, France Apr 16-20, 2007 Deadline: Sep 10, 2006 http://www.date-conference.com/ FPGA'07 -Int'l Symposium on Field-Programmable Gate Arrays Monterey, CA Feb 18-20, 2007 Deadline: Sep 15, 2006 http://conferences.ece.ubc.ca/isfpga2007/ IP-SOC'06 - IP Based SoC Design Grenoble, France Dec 6-7, 2006 Deadline: Sep 25, 2006 http://www.us.design-reuse.com/ipsoc2006/ ASYNC'07: Int'l Symposium on Asynchronous Circuits and Systems Berkeley, CA Mar 12-14, 2007 Deadline: Sep 25, 2006 http://conferences.computer.org/async2007/ ISQED'07 - Int'l Symposium & Exhibits on Quality Electronic Design San Jose, CA Mar 26-28, 2007 Deadline: Sep 30, 2006 http://www.isqed.org/ ISCAS'07 - Int'l Symposium on Circuits and Systems New Orleans, LA May 27-30, 2007 Deadline: Oct 6, 2006 http://www.iscas2007.org/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 Deadline: Oct 12, 2006 http://www.ispd.cc/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 Deadline: Oct 23, 2006 http://www.splconf.org/ GLSVLSI'07 - Great Lakes Symposium on VLSI Stresa-Largo Maggiore, Italy Mar 11-13, 2007 Deadline: Nov 10, 2006 http://www.glsvlsi.org/ DAC'07 - Design Automation Conference San Diego, CA Jun 4-8, 2007 Deadline: Nov. 20, 2006 http://www.dac.com/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 Deadline: Dec 1, 2006 http://www.nocsymposium.org/ ======================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 http://asap2006.grm.polymtl.ca/ ISOCC'06 - Int'l SoC Design Conference Seoul, Korea Oct 26-27, 2006 http://www.isocc.org/ ICCAD'06 - Int'l Conference on Computer-Aided Design San Jose, CA Nov 5-9, 2006 http://www.iccad.com/ PDCS'06 - Int'l Conference on Parallel and Distributed Computing and Systems Dallas, TX Nov 13-15, 2006 http://www.iasted.org/conferences/2006/Dallas/pdcs.htm CSS'06 - Conference on Circuits, Signals and Systems San Francisco, CA Nov 20-22, 2006 http://www.iasted.org/newsletter/2006/css2.htm IP-SOC'06 - IP Based SoC Design Grenoble, France Dec 6-7, 2006 http://www.us.design-reuse.com/ipsoc2006/ ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies: Theory and Applications Cairo, Egypt Jan 3-6, 2007 http://www.thetaconf.org VLSI'07 - Int'l Conference on VLSI Design Bangalore, India Jan 6-10, 2007 http://www.vlsiconference.com/2007/ ASPDAC'07 - Asia and South Pacific Design Automation Conference Yokohama, Japan Jan 23-26, 2007 http://www.aspdac.com/aspdac2007/ FPGA'07 -Int'l Symposium on Field-Programmable Gate Arrays Monterey, CA Feb 18-20, 2007 http://conferences.ece.ubc.ca/isfpga2007/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 http://www.splconf.org/ GLSVLSI'07 - Great Lakes Symposium on VLSI Stresa-Largo Maggiore, Italy Mar 11-13, 2007 http://www.glsvlsi.org/ ASYNC'07: Int'l Symposium on Asynchronous Circuits and Systems Berkeley, CA Mar 12-14, 2007 http://conferences.computer.org/async2007/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 http://www.ispd.cc/ DAC'07 - Design Automation Conference San Diego, CA Jun 4-8, 2007 http://www.dac.com/ ======================================================================== Upcoming funding opportunities ------------------------------- DOD Experimental and Theoretical Development of Quantum Information Science Deadline: December 11, 2006 http://www.arl.army.mil/main/Main/DownloadedInternetPages/CurrentPages/DoingBusinesswithARL/research/QC06Final6Jul06.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 NSF CISE Computing Research Infrastructure (NSF 06-597) Deadline: October 02, 2006 http://www.nsf.gov/pubs/2006/nsf06597/nsf06597.htm Computer Systems Research (CSR) (NSF 05-629) Deadline: Second Friday in November http://www.nsf.gov/pubs/2005/nsf05629/nsf05629.htm Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence (NSF 06-572) Deadline: October 19, 2006 for Large Projects November 02, 2006 for Medium Projects December 06, 2006 for Small Projects http://www.nsf.gov/pubs/2006/nsf06572/nsf06572.htm Cyber Trust (CT) (NSF 06-517) Deadline: First Monday in February http://www.nsf.gov/pubs/2006/nsf06517/nsf06517.htm Active Nanostructures and Nanosystems (ANN) (NSF 06-595) Deadline: November 15, 2006 http://www.nsf.gov/pubs/2006/nsf06595/nsf06595.htm Power, Controls and Adaptive Networks (PCAN) Deadline: September 7, 2006 - October 7, 2006 http://nsf.gov/funding/pgm_summ.jsp?pims_id=13380 Advanced Learning Technologies (ALT) (NSF 06-535) Deadline: April 25, 2007 http://www.nsf.gov/pubs/2006/nsf06535/nsf06535.htm Foundations of computing processes and Artifacts (NSF 06-585) Deadline: October 10, 2006 http://www.nsf.gov/pubs/2006/nsf06585/nsf06585.htm Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence (NSF 06-572) Full Proposal Deadline(s): October 19, 2006 for Large Projects November 02, 2006 for Medium Projects December 06, 2006 for Small Projects http://www.nsf.gov/pubs/2006/nsf06572/nsf06572.htm DARPA Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm NASA Applied Information Systems Research Deadline: January 30, 2007 http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId={0B64DB41-8F7D-C949-44CD-9D04A484B653}&path=open Fellowship Sloan Research Fellowships Deadline: September 15, 2006 http://www.sloan.org/programs/scitech_fellowships.shtml ======================================================================== Call For Papers ------------------------- ACM GLSVLSI 2007 Call For Papers http://www.glsvlsi.org/ The 17th edition of GLSVLSI will be held in Stresa - Lago Maggiore, Italy, the first time in Europe. Original, unpublished papers, describing research in the general area of VLSI are solicited. Both theoretical and experimental research results are welcome. Proceedings will be published by the ACM and will be included in the SIGDA compendium CD-ROM. Program Tracks * VLSI Design: design of ASICs, microprocessors and micro-architectures, embedded processors, analog/digital/mixed-signal systems, multi-chip modules, FPGAs. * VLSI Circuits: analog/digital/mixed-signal circuits, RF and communication circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits. * Computer-Aided Design (CAD): hardware/software co-design, logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction), algorithms and complexity analysis. * Low Power and Power Aware Design: circuits, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools. * Testing, Reliability, Fault-Tolerance: digital/analog/mixed-signal testing, design for testability and reliability, online testing techniques, static and dynamic defect- and fault-recoverability, and variation-aware design. * Emerging Technologies: nanotechnology, molecular electronics, quantum devices, biologically-inspired computing, single electron transistors, resonant tunneling devices, VLSI aspects of sensor and sensor network, and CAD tools for emerging technology devices and circuits. Best Student Paper Award A "Best Student Paper Award" will be voted on by the technical program committee. Only papers with a student as first author will be eligible. A laptop, generously donated by Intel, will be awarded to the winner at the symposium. Schedule * Paper Submission Deadline: November 10th, 2006 * Acceptance Notification: December 22nd, 2006 * Camera-Ready Paper Due: January 8th, 2007 ======================================================================== Call For Papers ----------------------- SELSE-3 Workshop April 3rd & 4th, 2007 Austin, Texas The growing complexity and shrinking geometries of modern device technologies are making these high-density, low-voltage devices increasingly susceptible to influences from electrical noise, process variation, and natural radiation interference. System-level effects of these errors can be far reaching. Growing concern about intermittent errors, erratic storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practices in system-level error management. Participants from industry and academia explore both current technologies and future research direction (including nanotechnology). We are interested in soliciting papers that cover system-level effects of errors from a variety of perspectives: architectural, logical and circuit-level, and semiconductor processes. Case studies are also solicited. Key areas of interest are (but not limited to): * Technology trends and the impact on error rates. * New error mitigation techniques. * Characterizing the overhead and design complexity of error mitigation techniques. * Case studies describing the engineering tradeoffs necessary to decide what mitigation technique to apply. * Experimental data. * System-level models: derating factors and validation of error models. * Error handling protocols (higher-level protocols for robust system design). Authors are requested to submit their extended abstracts for review before December 20, 2006. Guidelines for submission are available at www.selse.org. Submissions should be PDF or Microsoft Word files that do not exceed four printed pages. Customary terms for copyright agreement and non-confidentiality will apply. Authors will be notified of paper outcome by March 2, 2007. The camera-ready formatted papers are due on March 23, 2007. Registration information is posted on the workshop website: www.selse.org Organizing committee: Workshop Co-chairs Wendy Bartlett (HP) Pia Sanda (IBM) Program Co-chairs Dennis Abts (Cray) Subhasish Mitra (Stanford) Web Chair Jeff Wilkinson (Medtronic) Publications Chair Norbert Seifert (Intel) Publicity Co-Chairs Cristian Constantinescu (Intel) Babak Falsafi (CMU) Local Arrangements Chair Nur Touba (UT Austin) Finance Co-chairs Nhon Quach (AMD) Vivian Zhu (Texas Instr) Panel Co-Chairs Ishwar Parulkar (Sun) Josep Torrellas (Univ Illinois) Advisory Committee Sarita Adve (Univ Illinois) Ravi Iyer (Univ Illinois) Chuck Moore (AMD) Lisa Spainhower (IBM) ======================================================================== FOUNDATIONS AND TRENDS(r) IN ELECTRONIC DESIGN AUTOMATION ------------------------------------------------------------ FOUNDATIONS AND TRENDS(r) IN ELECTRONIC DESIGN AUTOMATION has just published its first issue: Languages and Tools for Hybrid Systems Design By Luca P. Carloni (Columbia University) Roberto Passerone (Cadence Berkeley Laboratories) Alessandro Pinto (University of California at Berkeley) Alberto L. Sangiovanni-Vincentelli (University of California at Berkeley) You can see the planned forthcoming articles and download this one for free at www.nowpublishers.com/EDA. If you or your library has a subscription, you'll be able to access future articles too. You can also purchase printed and bound versions of any of the published issues. You will receive a 45% discount on the list price (discount price is $66) by quoting the Promotion Code EDA001001 in the order form www.nowpublishers.com/bookorder.aspx?doi=1000000001&product=EDA ======================================================================== 5th SIGDA CADathlon at ICCAD 2006 --------------------------------- ACM/SIGDA Sponsors the Fifth Annual EDA Programming Contest at ICCAD Sunday, November 5, 2006, 8:00 AM - 5:00 PM The CADathlon is a challenging, all-day, programming competition focusing on practical problems at the forefront of Electronic Design Automation. The contest emphasizes the knowledge of algorithmic techniques for CAD applications, problem-solving and programming skills, as well as teamwork. In its fifth year as the Olympic games of EDA, the contest brings together the best and the brightest of the next generation of CAD professionals. It gives the academia and the industry a unique perspective on challenging problems and rising stars, and it also attracts top graduate students to the EDA field. The contest is open to 2-person teams where each member is currently enrolled as full-time Ph.D. students in any country. Each team must submit an on-line application by September 29, 2006. Students will be selected based on their academic and course backgrounds, and their relevant EDA programming experiences. Several travel grants will be provided to qualifying students. The CADathlon competition consists of six problems in the following areas: (1) circuit analysis, (2) physical design, (3) logic and behavioral synthesis, (4) system design and analysis, (5) functional verification, and (6) timing, test, and manufacturing. More specific information about the problems and relevant research papers will be released on the Internet one week prior to the competition. The writers and judges that construct and review the problems are experts in EDA from both academia and industry. At the contest, students will be given the problem statements and example test data, but they will not have the judges' test data. Solutions will be judged on correctness and efficiency. Where appropriate, partial credit might be given. The team that earns the highest score is declared the winner. In addition to handsome trophies, the first prize is a $2,000 cash award. The second prize is a $1,000 cash award. Past winners include teams from UC Berkeley, University of Michigan, and MIT. The CADathlon competition is sponsored by ACM/SIGDA and several EDA companies. For detailed contest information and sample problems from last year's competition, please visit the ACM/SIGDA web site: http://www.sigda.org/programs/cadathlon You are also invited to contact the CADathlon organizing committee chair Dr. Geert Janssen . ======================================================================== *EXTENDED* Advance Registration Deadline for *ISLPED 2006* ------------------------------------------------------------ Take advantage of reduced rates until *Sept.8*, 2006 for symposium registration and *Sept.10*, 2006 for hotel rates Register for *three exciting tutorials* in the area of system level, on-chip power and variability implications, analog power optimization, and leakage power: (1) *Ship Defective Chips and Live to Tell the Story: Variability, Noise, and Power Considerations in On-chip Computation and Communication* http://www.islped.org/tutorials/tutorial1.pdf Radu Marculescu, Carnegie Mellon University, Pittsburgh, PA Peter Feldmann, IBM Research, Yorktown, NY (2) *Design Methods for Minimizing Thermal and Flicker Noise at Minimum Power Consumption in Micropower CMOS Circuits* http://www.islped.org/tutorials/tutorial2.pdf David Binkley, U. of North Carolina, Charlotte, NC (3) *Leakage Currents in Nanometer CMOS* http://www.islped.org/tutorials/tutorial3.pdf Domenik Helms, Wolfgang Nebel, OFFIS Ali Keshavarzi, Intel Corp. ======================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ======================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. First time users will be required to choose a password.) ========================================================================