======================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org ======================================================================== 15 July 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 14 Online archive: http://www.sigda.org/newsletter ======================================================================== Contents of this E-NEWSLETTER: (1) Letter From The Chair Diana Marculescu (2) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Upcoming Funding Opportunities Qinru Qiu (6) Call For Participation HOT Chips 18: A Symposium on High-Performance Chips Alan Smith (7) Call For Papers The 13th IEEE* International Symposium on Asynchronous Circuits and Systems Ran Ginosar (8) Call For Participation The 2006 Federated Logic Conference ======================================================================== Dear ACM/SIGDA members, As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; ======================================================================== Letter From The Chair ---------------------------- Dear ACM/SIGDA Members, As with every Summer since 43 years ago, comes the long-awaited ACM/IEEE Design Automation Conference. ACM/SIGDA has been a sponsor of the Design Automation Conference since its inception and continues to augment its technical and exhibiting activities with programs run by SIGDA. As in the past years, we welcome all DAC attendees at SIGDA-sponsored events: * on Tuesday evening (July 25th, 6:30-8pm, Rm. 310 @ Moscone Center), students will showcase their dissertation work in the 9th SIGDA Ph.D. Forum at DAC (http://www.sigda.org/daforum); * demos of University research projects are presented in the 19th SIGDA University Booth (Booth 1006) every day on the exhibit floor (http://www.sigda.org/programs/UniversityBooth/Ubooth2006/). We invite you to attend these events and programs along with other colleagues and friends! 2006 is a special year . that of SIGDA Newsletter.s 35th Anniversary. Started 35 years ago in 1971, the SIGDA Newsletter has been the home for early technical EDA articles and news from the EDA industry. Now distributed electronically, the Newsletter has been revamped over the years and has become a reference for EDA news for professionals from industry and academia. The new .What is.... column is a welcomed addition that was recently inaugurated with the new editorial board. Look for the ACM/SIGDA flyer in your DAC attendee bag where you will find excerpts from the first issue of this new column, along with Newsletter samples from the past. In the flyer you will also find a SIGDA/DAC trivia contest - winners receive a FREE SIGDA MEMBERSHIP for 2007 which comes with: * reduced registration rates at SIGDA-sponsored conferences; * eligibility for SIGDA travel grants; * yearly conference Supercompendium DVD; * THIS newsletter in your mailbox every two weeks. We hope you will all join us at DAC! Diana Marculescu SIGDA Chair ======================================================================== SIGDA News ----------------------- "Metcalfe's Law is Wrong" http://www.spectrum.ieee.org/jul06/4109 The well-known Metcalfe's law claims that the value of a network grows as the square of its size, and has been used to make a number of technology and economic projections. However, the authors point out that this function fails basic sanity checks, while the logic justifying its use makes unrealistic assumptions. They argue that the NlogN function of the network's size estimates the network's value much better. "A Wireless Chip the Size of Grain!" http://www.techtree.com/techtree/jsp/article.jsp?article_id=74655&cat_id=581 "Memory Spot", a research team at HP Labs, has developed a wireless data chip about the size of a grain of rice (2 mm to 4 mm square). HP claims that the chip has a ten megabits-per-second data transfer rate, which is ten times faster than Bluetooth wireless technology, and comparable to Wi-Fi speeds, giving users instant retrieval of information in audio, video, photo, or document form. With a storage capacity ranging from 256 kilobits to 4 megabits in working prototypes, the device can store a very short video clip, several images, or dozens of pages of text. These chips will eventually be made available as a booklet with self-adhesive dots. "100-Mbps Broadband: How, Why, When, and Where?" http://www.edn.com/article/CA6347250.html Long the Holy Grail for telecom companies and MSOs (multiple-service operators), or cable companies, the triple play succinctly means serving consumers' voice, video, and data needs over a converged network. And without question, some telecom companies and MSOs are delivering today. "Seth Lloyd: Is The Universe A Quantum Computer?" http://www.technologyreview.com/read_article.aspx?id=17091&ch=infotech Seth Lloyd, a professor of mechanical engineering at MIT, is among the pioneers of quantum computing: he proposed the first technologically feasible design for a quantum computer. If humans ever build a useful, general-purpose quantum computer, it will owe much to Lloyd. Earlier this year, he published a popular introduction to quantum theory and computing, titled /Programming the Universe/, which advanced the startling thesis that the universe is /itself/ a quantum computer. "The $100 Laptop Initiative from MIT (One Laptop Per Child)" http://www.todaysengineer.org/2006/Jul/laptop.asp The article is written by the CTO of the One Laptop Per Child organization, which is supported by the UN, AMD, Nortel Networks, Google, eBay, UL, 3COM, Marvel and many others. It describes ongoing work and early successes in designing a $100 laptop that would consume 1/10 power of a typical laptop (2W), have 3-4X the range of typical laptop WiFi antennae (~1Km), have no moving parts, include a high-resolution monitor, work off multiple power sources (car adapter, etc) or human-powered battery recharge, be water-resistant and dust-proof. A number of large countries, such as Brasil, Argentina and Nigeria have promised to buy at least a million each. "DFM Startup Targets 'Hot Spot' Detection, Repair" http://www.eetimes.com/showArticle.jhtml?articleID=190302479 Design-for-manufacturability (DFM)-focused startup Takumi Technology Corp. introduced a pair of new products designed to optimize IC physical design and enhance yields. The tools, Takumi Inspect and Takumi Enhance, are said to detect, rate and automatically repair hot spots in sub-90 nm designs. Takumi Inspect is a layout analysis software tool that detects yield-impacting problems in GDSII layouts, then rates them in terms of probability of failure, according to Takumi. Takumi Enhance is an automated physical design optimization system that rates GDS layouts for potential failures, prioritizes the failure mechanisms, and uses optimization techniques to repair the layout against multiple failure mechanisms to provide "hot spot-free" designs, the company said. "Lithography Vendors Unveil Next-Generation Scanners" http://www.eetasia.com/ARTP_8800425484_480200.HTM The bell has sounded for leading-edge lithography vendors, which are coming to market with next-generation immersion scanners for the 45nm node and beyond. Enabling the next wave of chip designs, Japan's Nikon Inc. recently unveiled a 193nm immersion lithography scanner that is equipped with a hyper-numerical-aperture (NA) projection lens, rated at 1.3. Rival ASML Holding NV is expected to unwrap details of a yet-to-be-announced 193nm immersion lithography system dubbed the XT:1900i, sources said. Not to be outdone, Japan's Canon Inc. is expected to disclose the details of its initial immersion lithography system, sources added. In immersion lithography, the space between the projection lens and the wafer is filled with water. Immersion technology is expected to offer a better depth of focus over conventional, "dry" lithography scanners. The technology could potentially extend 193nm tools down to 32nm, according to analysts. While immersion lithography is slowly making its way into production fabs, there is a growing concern about the cost-of-ownership issues associated with the newfangled systems. "Chartered Begins 90-nm Manufacturing for AMD" http://www.eetimes.com/showArticle.jhtml?articleID=190400017 Advanced Micro Devices Inc. said Thursday (July 13) that Singapore-based foundry Chartered Semiconductor Manufacturing Co. Ltd. has started making AMD64 microprocessors using 90-nm design rules at Chartered's 300-mm fab. The companies said they plan to begin using 65-nm design rules in mid-2007. In 2004, Chartered joined an alliance based in Fishkill, N.Y. with IBM and AMD to develop 65- and 45-nm SOI processes. IBM and AMD use an SOI-based process for their microprocessors. Also in 2004, Chartered took a license for the 90-nm SOI process codeveloped by IBM and AMD. "MRAM Used for High Speed Embedded Memory" http://www.electronicsweekly.com/Articles/Article.aspx?liArticleID=39236&PrinterFriendly=true NEC says it has developed a version of MRAM which is suitable for embedding in Asics. The NEC MRAM cell has three elements; a 2T1MTJ (two transistors and one magnetoresistive tunnelling junction) cell structure to accelerate write mode cycle time, a 5T2MTJ cell structure to accelerate read mode cycle time, and a write-line-inserted MTJ to reduce write current. NEC says it is a suitable replacement for SRAMs for implementing macros in Asics. The problem with MRAM as a potential memory for embedding in Asics is that it has been too slow compared to SRAM which has been the traditional memory technology for embedded applications. NEC's MRAM delivers a 200MHz random access write. Elimination of the upper limit of the writing current by a 2T1MTJ cell enables high speed. In conventional MRAM memory cells, writing current must be within upper and lower limits preventing it from operating at over 100MHz. "The Future of Human-Computer Interaction" http://www.acmqueue.com/modules.php?name=Content&pa=printer_friendly&pid=402&page=1 Is an HCI revolution just around the corner? Personal computing launched with the IBM PC. But popular computing - computing for the masses - launched with the modern WIMP (windows, icons, mouse, pointer) interface, which made computers usable by ordinary people. As popular computing has grown, the role of HCI (human-computer interaction) has increased. "Evolution or Revolution?" http://www.acmqueue.com/modules.php?name=Content&pa=printer_friendly&pid=384&page=1 Where is the High in High Tech? We work in an industry that prides itself on changing the world, one that chants a constant mantra of innovation and where new products could aptly be described as this year's breakthrough of the century. While there are some genuine revolutions in the technology industry, including cellphones, GPS (global positioning system), quantum computing, encryption, and global access to content, the vast majority of new product introductions are evolutionary, not revolutionary. Real technical breakthroughs are few and far between. Most new products are just a recycling of an earlier idea. "It's Time to Abstract Higher-Levels of Performance From Your Verification Process" http://www.chipdesignmag.com/display.php?articleId=476 Webster defines a system as: "A group of interacting, interrelated, or interdependent elements forming a complex whole." In electronics, the distinction between chips and systems has been blurred, but one thing is clear - systems tend to be a heterogeneous mix of processors, peripherals, third-party IP blocks, random logic, memory, embedded software, and analog functions. "Is Chip Design Different After 90 nm?" http://www.edn.com/article/CA6347251.html At every new process node, IC design becomes more difficult. But, as design teams contemplate the move to 90- and then 65-nm-process nodes, many are asking whether the increased difficulty is still just a matter of degree or whether something fundamental is changing. Does a successful 90-nm-design team differ in some way from a successful 130-nm-design team? If so, is the change a one-time thing, or are the differences even greater at 65 nm? The only way to find out is to talk to successful design teams. "Using A Multicore RTOS for DSP Applications" http://www.embedded.com/shared/printableArticle.jhtml?articleID=190500287 Semiconductor companies continue to shrink the minimum feature size of their processors, pack an exponentially increasing number of transistors onto a single die, and increase clock speeds. As a result, the industry has reached a turning point where the power dissipation of the device has become a limiting factor for processor speed. "Exclusive Presentation by Renowned EDA Researcher" http://www.electronicstalk.com/news/xoo/xoo102.html* *Xoomsys, a Silicon Valley company focused on offering scalable performance for accurate circuit simulation, has announced that it will host an exclusive presentation to be given by renowned EDA researcher Dr Resve Saleh at the Design Automation Conference being held on July 24 - 28, 2006 in San Francisco, Calif. Dr Saleh will present 'Dynamic Coupling Problems in Nanometer Design' on Tuesday, July 25 and Wednesday, July 26 at 2:00pm at the Xoomsys booth #1624 South Hall,Moscone centre. Dr Saleh will describe the growing crisis of dynamic coupling, and its impact on silicon success. "TSMC Reference Flow 7.0 Incorporates Synopsys' IC Compiler" http://biz.yahoo.com/prnews/060718/sftu053.html?.v=61 MOUNTAIN VIEW, Calif. and HSINCHU, Taiwan, July 18: Synopsys, Inc. (Nasdaq: SNPS - News ), a world leader in semiconductor design software, and Taiwan Semiconductor Manufacturing Company (NYSE: TSM - News ) -- the world largest semiconductor foundry, today announced Synopsys' Galaxy(TM) design and DFM platforms support in TSMC's Reference Flow 7.0. The Reference Flow 7.0 includes Synopsys' IC Compiler next-generation physical implementation to provide new low-power and yield capabilities that address 65-nanometer design challenges. This collaborative effort between the two companies brings together advanced semiconductor design and manufacturing to achieve optimum IC performance, power, and yield with higher predictability. "Silicon Photonics Enters The Broadband Age" http://optics.org/optics/Articles.do?type=news&volume=12&issue=7&article=17&page=1 Photonic microchips are one step closer to emulating their electronic counterparts now that researchers at Cornell University , New York, have produced a broadband light amplifier on a silicon chip. The device, which relies on microscopic waveguides rather than wires, will help pave the way to super-fast transmission on silicon. ======================================================================== Submission deadlines: --------------------- ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies: Theory and Applications Cairo, Egypt Jan 3-6, 2007 Deadline: Jul 17, 2006 http://www.thetaconf.org/ ISLPED'06 - Int'l Low Power Design Contest Tegernsee, Germany Oct 4 - 6, 2006 Deadline: Jul 31, 2006 http://www.islped.org/contest.html DATE'07 - Design Automation and Test in Europe Nice, France Apr 16-20, 2007 Deadline: Sep 10, 2006 http://www.date-conference.com/ IP-SOC'06 - IP Based SoC Design Grenoble, France Dec 6-7, 2006 Deadline: Sep 25, 2006 http://www.us.design-reuse.com/ipsoc2006/ ISCAS'07 - Int'l Symposium on Circuits and Systems New Orleans, LA May 27-30, 2007 Deadline: Oct 6, 2006 http://www.iscas2007.org/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 Deadline: Oct 12, 2006 http://www.ispd.cc/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 Deadline: Oct 23, 2006 http://www.splconf.org/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 Deadline: Dec 1, 2006 http://www.nocsymposium.org/ ======================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- DAC'06 - Design Automation Conference San Francisco, CA Jul 24-28, 2006 http://www.dac.com/ DAC'06 - SIGDA Ph.D. Forum at DAC San Francisco, CA Jul 25, 2006 http://www.sigda.org/daforum/ EUC'06 - Int'l Conference on Embedded And Ubiquitous Computing Seoul, Korea Aug 1-4, 2006 http://euc06.euc-conference.org/ MWSCAS'06 - Int'l Midwest Symposium on Circuits and Systems San Juan, Puerto Rico Aug 6-9, 2006 http://mwscas06.ece.uprm.edu/ EC'06 - Int'l Workshop on Embedded Computing Columbus, OH August 14, 2006 http://juliet.stfx.ca/~lyang/icpp06-ec/ ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 http://asap2006.grm.polymtl.ca/ ISOCC'06 - Int'l SoC Design Conference Seoul, Korea Oct 26-27, 2006 http://www.isocc.org/ ICCAD'06 - Int'l Conference on Computer-Aided Design San Jose, CA Nov 5-9, 2006 http://www.iccad.com/ PDCS'06 - Int'l Conference on Parallel and Distributed Computing and Systems Dallas, TX Nov 13-15, 2006 http://www.iasted.org/conferences/2006/Dallas/pdcs.htm ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies: Theory and Applications Cairo, Egypt Jan 3-6, 2007 http://www.thetaconf.org VLSI'07 - Int'l Conference on VLSI Design Bangalore, India Jan 6-10, 2007 http://www.vlsiconference.com/2007/ ASPDAC'07 - Asia and South Pacific Design Automation Conference Yokohama, Japan Jan 23-26, 2007 http://www.aspdac.com/aspdac2007/ ISPD'07 - Int'l Symposium on Physical Design Austin, TX Mar 18-21, 2007 http://www.ispd.cc/ ======================================================================== Upcoming funding opportunities ------------------------------- SRC Integrated Circuit and Systems Sciences (ICSS) - Circuit Design Deadline: August 18, 2006 http://www.src.org/fr/current_calls.asp?bhcp=1 Integrated Circuit and Systems Sciences (ICSS) - Integrated Systems Design Deadline: August 18, 2006 http://www.src.org/fr/current_calls.asp?bhcp=1 DOD Experimental and Theoretical Development of Quantum Information Science Deadline: December 11, 2006 http://www.arl.army.mil/main/Main/DownloadedInternetPages/CurrentPages/DoingBusinesswithARL/research/QC06Final6Jul06.pdf Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html Joint National Training Capability Broad Agency Announcement Deadline: May 14, 2009 http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 Optoelectronics: Components and Information Processing Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/optoelectronics.htm Software and Systems Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/software_and_systems.htm Information Fusion and Artificial Intelligence Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/information_fusion.htm Computational Mathematics Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/computational_mathematics.htm Electronics Design for Cold Environments (CRREL-66) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf Sensors, Sensor Systems, Data Acquisition, Processing, and Transmission Systems (ITL-6) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf High Performance Computing (HPC) and Networking (ITL-4) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf NSF Power, Controls and Adaptive Networks (PCAN) Deadline: September 7, 2006 - October 7, 2006 http://nsf.gov/funding/pgm_summ.jsp?pims_id=13380 Advanced Learning Technologies (ALT) (NSF 06-535) Deadline: April 25, 2007 http://www.nsf.gov/pubs/2006/nsf06535/nsf06535.htm Foundations of computing processes and Artifacts (NSF 06-585) Deadline: October 10, 2006 http://www.nsf.gov/pubs/2006/nsf06585/nsf06585.htm Instrument Development for Biological Research (IDBR) (NSF 06-570) Deadline: August 25, 2006 http://www.nsf.gov/pubs/2006/nsf06570/nsf06570.htm Operations Research (OR) Deadline: September 1, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13341&org=NSF&from=fund Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence (NSF 06-572) Full Proposal Deadline(s): October 19, 2006 for Large Projects November 02, 2006 for Medium Projects December 06, 2006 for Small Projects http://www.nsf.gov/pubs/2006/nsf06572/nsf06572.htm DARPA TRUST for Integrated Circuits (BAA06-40) Original Response Date: Aug 11, 2006 http://www.darpa.mil/baa/baa06-40.html Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm Advanced Soldier Sensor Information System and Technology Deadline: August 04, 2006 http://fedbizopps.cos.com/cgi-bin/eps/spg/ODA/DARPA/CMO/BAA04-38/listing.html?notice=MOD NASA Applied Information Systems Research Deadline: January 30, 2007 http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId={0B64DB41-8F7D-C949-44CD-9D04A484B653}&path=open DOE Solid-State Lighting Core Technologies Deadline: June 27, 2006 https://e-center.doe.gov/iips/faopor.nsf/3b3cff0a4a1f243485256ec100490e1a/3d84c25df7cf18428525716c006d1004?OpenDocument Fellowship Sloan Research Fellowships Deadline: September 15, 2006 http://www.sloan.org/programs/scitech_fellowships.shtml ======================================================================== Call For Participation ----------------------------- HOT Chips 18 ADVANCE PROGRAM A Symposium on High-Performance Chips August 20-22, 2006, Memorial Auditorium, Stanford University, Palo Alto, California http://www.hotchips.org HOT Chips brings together designers and architects of high-performance chips, software, and systems. Presentations focus on up-to-the-minute real developments. This symposium is the primary forum for engineers and researchers to highlight their leading-edge designs. Three full days of tutorials and technical sessions will keep you on top of the industry. See http://www.hotchips.org for registration information, local arrangements, location, etc. ------------------------- Sunday, August 20, 2006 ------------------------- Morning Tutorial: Multicore Programming: From Threads to Transactional Memory Yuan Lin (Sun Microsystems) Christos Kozyrakis (Stanford) Ali-Reza Adl-Tabatabai (Intel) Bratin Saha (Intel) Afternoon Tutorial Wireless in the home - Challenges and Opportunities Jan Rabaey (UC Berkeley) ------------------------- Monday, August 21, 2006 ------------------------- Video Processing (Phillips Semiconductors) * Highly Integrated Nexperia PNX8535 Hybrid TV Processor * Heterogeneous Multiprocessing for Multi-Std HD Video Decoding * Home Entertainment-Quality on the Move: Nexperia PNX4103 Keynote I: Justin Rattner, Intel Sr. Fellow, Chief Technology Officer * Cool Codes for Hot Chips Microprocessors I * The Low-Power High-Perf. Arch. of the PWRficient Processor Family (P.A. Semi) * The Opteron CMP NorthBridge Architecture, Now and in the Future (AMD) Memory and Storage * Z-RAM Ultra-dense memory for 90nm and below (Innovative Silicon) * The Ultra Small HDD for the Mobile Applications (Toshiba) Reconfigurable Computing * Virtex5, the Next Generation 65nm FPGA (Xilinx) * RAMP: Research Accelerator for Multiple Processors UC Berkeley, CMU, Intel, MIT, UT Austin, Stanford, U. Wash.) * A Dynamically Reconfigurable HW Accelerator (Toshiba) Parallel Processing * TeraOPS: A Massively-Parallel, MIMD Computing Fabric IC (Ambric) * CA1024: Programmable SOC for HDTV Media Processing (Connex Tech.) * AsAP: An Asynchronous Array of Simple Processors (UC Davis) Panel: Who owns the living room? Moderator: Jan-Willem van de Waerdt (Philips Semiconductors) James Akiyama (Intel) Bob Brummer (Microsoft) Bill Curtis (Dell) Eugene Shteyn (Philips CE) Alan Messer (Samsung) Glen Stone (Sony) Prof. Yamada (Kyushu Institute of Technology) ------------------------- Monday, August 21, 2006 ------------------------- Embedded Processors * ARM996HS: First Licensable, Clockless 32-bit Processor Core (Handshake Solutions) * MIPS32(r) 34K(tm) Cores: Ultimate Flexibility for Embedded Apps (MIPS) * A Reusable 1GHz Super-scalar ARM Processor (ARM) * Towards Optimal Custom Instruction Processors (Imperial College) Keynote II: Bernard Meyerson, IBM Fellow; VP Strategic Alliances and Chief Technologist * Collaborative Innovation: A New Lever in Information Technology Development Novel Silicon Applications * In Silico Vox: Toward Speech Recognition in Silicon (Carnegie Mellon) * Processor Architecture for High-Performance Stream Processing (IBM Zurich) * Micro Manipulator Array for the Nano-bioelectronics Era (Toshiba) Communications * FocalPoint: A Low-Latency, High-Bandwidth Ethernet Switch (Fulcrum Micro.) * SH-MobileG1: A Single-Chip Application & Dual-Mode Baseband (Renesas) * APP300 Access Network Processor (Agere Systems) Microprocessors II * TULSA: A Dual P4 Core Large Shared Cache Intel(r) Xeon(tm) Processor (Intel) * Niagara2: A Highly-Threaded Server-on-A-Chip (Sun Micro) * Blackford: A Dual Processor Chipset for Servers & Workstations (Intel) * Inside the Core(tm) Microarchitecture (Intel) This is a preliminary program; changes may occur. For the most up-to-the-minute details on presentations and schedules, and for registration information, please visit our web site where you can also check out HOT Interconnects (another HOT Symposium being held following HOT Chips): Web: http://www.hotchips.org Email: info2006@hotchips.org Organizing Committee General Chair: Yusuf Abdulghani Apple Vice Chair: John Sell Microsoft Finance: Lily Jow HP Publicity: Donna Wilson Donna Wilson & Assoc. Gail Sachs Telairity Advertising: Don Draper Rambus Sponsorship: Amr Zaky Broadcom Publications: Gordon Garb GHI Registration: Ravi Rajamani Sun Sujata Ramasubramanian Intel Local Arrangments: Lance Hammond Apple Allen Baum Intel Charlie Neuhauser Neuhauser Assoc. Webmaster: Alexis Cordova Steering: Don Alpert Camelback Arch. Lily Jow HP John Mashey Techviser Howard Sachs Telairity Alan Jay Smith UC Berkeley At Large: Slava Mach Bob Stewart SRE Program Committee Co-Chairs: John Kubiatowicz UC Berkeley Howard Sachs Telairity Program Committee: Rajeevan Amirtharajah UC Davis Forrest Baskett NEA Bill Dally Stanford Pradeep Dubey Intel David Kirk nVIDIA Christos Kozyrakis Stanford Chuck Moore AMD Mitso Saito Toshiba Alan Jay Smith UC Berkeley Marc Tremblay Sun Micro. Jan-Willem van de Waerdt Philips Semiconductors John Wawrzynek UC Berkeley A Symposium of the Technical Committee on Microprocessors and Microcomputers of the IEEE Computer Society ======================================================================== Call For Papers ----------------------------- The 13th IEEE* International Symposium on Asynchronous Circuits and Systems http://conferences.computer.org/async2007/ The International Symposium on Asynchronous Circuits and Systems provides a high-quality forum for scientists and engineers to present their latest research findings. Authors are invited to submit full papers on all aspects of asynchronous design. Topics of interest include, but are not limited to: . Mixed synchronous/asynchronous architectures, interfaces, andcircuits. . High-speed/low-power asynchronous logic, memories, and interconnects. . High-level design and synthesis of self-timed circuits. . Physical design of unclocked logic and pipelines. . Formal methods for correctness and performance analysis of asynchronous designs. . Test, reliability, security, and radiation tolerance. . CAD for asynchronous design and validation. . Asynchronous System-on-Chip (SoC), System-in-Package (SiP), and Network-on-Chip (NoC). . Novel asynchronous architectures. . Asynchrony and latency tolerance in system-level design. Papers should be submitted via the conference web site. The submission should not exceed ten pages in IEEE double-column format. Papers that exceed the length limit may not be reviewed. Papers will be evaluated by the program committee and reviews will be based on scientific merit, innovation, relevance, and presentation. New-idea papers are encouraged, and the program committee recognizes that such papers may contain less evaluation than papers in established areas. Accepted papers will be published in an IEEE proceedings and distributed at the symposium. Please check the symposium website for up-to-date information: http://conferences.computer.org/async2007 Paper Schedule: * Submission deadline: September 25, 2006 * Notification of acceptance: November 20, 2006 * Final version due: December 20, 2006 General Chairs Peter Beerel, Univ. of Southern California Marly Roncken, Intel Program Chairs Mark Greenstreet, Univ. of British Columbia Montek Singh, U. of N. Carolina, Chapel Hill Publications Erik Brunvand, Univ. of Utah Best Paper Award H. Peter Hofstee, IBM Research Invited Speakers and Tutorials Jan Rabaey, Univ. Calif. Berkeley Ivan Sutherland, Sun Microsystems Publicity Ran Ginosar, Technion, Israel Industrial Liaisons Ken Stevens, Univ. of Utah Pascal Vivet, CEA-LETI, Grenoble Finance Peter Beerel, Univ. of Southern California Local Arrangements Jeff Rulifson, Sun Microsystems ======================================================================== Call For Participation ----------------------- The 2006 Federated Logic Conference Seattle, Washington, USA August 10 -- August 22, 2006 http://www.easychair.org/FLoC-06/ Early registration deadline: July 10, 2006. We are pleased to announce the fourth Federated Logic Conference (FLoC'06) to be held in Seattle, Washington, in August 2006, at the Seattle Sheraton (http://www.easychair.org/FLoC-06/floc-hotel.html). FLoC'06 promises to be the premier scientific meeting in computational logic in 2006. The following conferences will participate in FLoC'06: CAV Conference on Computer Aided Verification (Aug 17-20) ICLP Int'l Conference on Logic Programming (Aug 17-20) IJCAR Int'l Joint Conference on Automated Reasoning (Aug 17-20) LICS IEEE Symposium on Logic in Computer Science (Aug 12-15) RTA Conference on Rewriting Techniques and Applications (Aug 12-14) SAT Int'l Conference on Theory and Applications of Satisfiability Testing (Aug 12-15) The six major conferences will be accompanied by 41 workshops, held on Aug. 10-11, 15-16, and 21-22. The FLoC'06 program includes a keynote session to commemorate the Goedel Centenary, with John Dawson and Dana Scott as speakers, a keynote talk by David Harel, plenary talks by Randy Bryant and David Dill, and invited talks by F. Bacchus, A. Blass, B. Buchberger, A. Darwiche, M. Das, J. Esparza, J. Giesl, A. Gordon, T. Hoare, O. Kupferman, M. Lam, D. Miller, K. Sakallah, J. Stoy, and C. Welty. Seattle, the Emerald city, sits on the shores of Puget Sound surrounded by mountains to the east and west. Lovely views of blue waters and snow capped peaks seem to appear everywhere - around the next bend in the road or between the buildings downtown. Seattle is the gateway to the Pacific Northwest, a premier tourist attraction. In Seattle, Mt. Rainier enchants visitors; in Vancouver, British Columbia, the Coast Range juts out over downtown; and in Portland, 5,000 acres of forestland north of the city center harbor deer, elk, and the odd bear and cougar. Online registration for FLoC is now open at: http://www.easychair.org/FLoC-06/ Deadline for early registration is July 10, 2006. The rates agreed upon between FLoC and the Seattle Sheraton are very reasonable rates for a first-class hotel in downtown Seattle during the summer vacation season. To reduce conference costs and keep registration fees reasonable, FLoC is contractually obligated to meet a commitment for a certain number of FloC attendees staying in the conference hotel. FLoC attendees are strongly encouraged to use the Seattle Sheraton for conference accommodation. Deadline for preferred hotel rate is July 21, 2006. FLoC'06 Steering Committee Moshe Y. Vardi (General Chair) Thomas Ball (Conference Co-Chair) Jakob Rehof (Conference Co-Chair) Edmund Clarke (CAV) Reiner Hahnle (IJCAR) Manuel Hermenegildo (ICLP) Phokion Kolaitis (LICS) Henry Kautz (SAT) Aart Middeldorp (RTA) Andrei Voronkov (IJCAR) ======================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ========================================================================