======================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org ======================================================================== 1 July 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 13 Online archive: http://www.sigda.org/newsletter ======================================================================== Contents of this E-NEWSLETTER: (1) Letter From The Chair Diana Marculescu (2) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Upcoming Funding Opportunities Qinru Qiu (6) Call For Papers The 13th IEEE* International Symposium on Asynchronous Circuits and Systems Ran Ginosar (7) Call for Participation The 2006 Federated Logic Conference (8) Call For Nominations 2006 ACM Outstanding Ph.D. Dissertation Award in EDA Radu Marculescu (9) Call For Nominations 2006 SIGDA Outstanding New Faculty Award Martin D.F. Wong ======================================================================== Dear ACM/SIGDA members, As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; ======================================================================== Letter From The Chair ---------------------------- Dear ACM/SIGDA Members, As with every Summer since 43 years ago, comes the long-awaited ACM/IEEE Design Automation Conference. ACM/SIGDA has been a sponsor of the Design Automation Conference since its inception and continues to augment its technical and exhibiting activities with programs run by SIGDA. As in the past years, we welcome all DAC attendees at SIGDA-sponsored events: * on Tuesday evening (July 25th, 6:30-8pm, Rm. 310 @ Moscone Center), students will showcase their dissertation work in the 9th SIGDA Ph.D. Forum at DAC (http://www.sigda.org/daforum); * demos of University research projects are presented in the 19th SIGDA University Booth (Booth 1006) every day on the exhibit floor (http://www.sigda.org/programs/UniversityBooth/Ubooth2006/). We invite you to attend these events and programs along with other colleagues and friends! 2006 is a special year . that of SIGDA Newsletter.s 35th Anniversary. Started 35 years ago in 1971, the SIGDA Newsletter has been the home for early technical EDA articles and news from the EDA industry. Now distributed electronically, the Newsletter has been revamped over the years and has become a reference for EDA news for professionals from industry and academia. The new .What is.... column is a welcomed addition that was recently inaugurated with the new editorial board. Look for the ACM/SIGDA flyer in your DAC attendee bag where you will find excerpts from the first issue of this new column, along with Newsletter samples from the past. In the flyer you will also find a SIGDA/DAC trivia contest - winners receive a FREE SIGDA MEMBERSHIP for 2007 which comes with: * reduced registration rates at SIGDA-sponsored conferences; * eligibility for SIGDA travel grants; * yearly conference Supercompendium DVD; * THIS newsletter in your mailbox every two weeks. We hope you will all join us at DAC! Diana Marculescu SIGDA Chair ======================================================================== SIGDA News ----------------------- "AMD to Build a 32nm Fab in Upstate NY" http://www.eetimes.com/showArticle.jhtml?articleID=189601106 AMD announced plans for build a 300-mm fab. The most likely location is in the Luther Forest Technology Park in Saratoga County in upstate New York. Construction will start in 2007, and the plan should be operational in 2010. With a price tag of $3.5B, the plant is widely expected to produce 32nm chips. "Power Management Chip" http://www.wirelessdesignmag.com/ShowPR.aspx?PUBCODE=055&ACCT=0031599&ISSUE=0606&RELTYPE=PP&PRODCODE=Q0170&PRODLETT=A Freescale Semiconductor is meeting the increasing demands to power new features in today's smart mobile devices with this highly integrated power management and user interface (PMUI) chip. With this single-chip device, designers can optimize system power and drive a variety of powerful audio and multimedia features in products such as 3G phones, mobile gaming units and portable media players. "DFM Startup Aims for Worst Cases" http://www.eetimes.com/showArticle.jhtml?articleID=190100054 One of the foundations of nanometer IC design is the availability of accurate, worst-case inter- connect models for delay, crosstalk and IR drop. Design-for-manufacturability (DFM) startup Nanno Solutions believes it has found a fast and accurate way to bring those models into the design flow. Nanno Solutions this week will announce the company's opening and its first two products. Using a proprietary way of speeding up Monte Carlo simulation, Nanno-Win generates statistically based interconnect models. The Nanno-Cal calculator then takes those models and generates resistance-capacitance-inductance netlists for floor planners, circuit simulators and delay estimators. "Cooley Census: Magma Users Prefer Anonymity" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=189601468 While EDA users responding to /Deepchip.com/ moderator John Cooley's latest "Everything Else EDA Census" offer positive reviews of most Magma Design Automation Inc. tools, Cooley flags an interesting trend-most prefer to remain anonymous. "Simulating Quantum Interactions of Metal Atoms on BlueGene L" http://www.insidebayarea.com/dailyreview/localnews/ci_3966569 Researchers at the Lawrence Livermore nuclear weapons lab have set a new record for software speed, using the world's most powerful computer to simulate the quantum interactions of metal atoms at more than 200 trillion calculations per second. The simulation modeled the behavior of 1,000 atoms of half-molten molybdenum, a piece of matter smaller than a DNA strand and undetectable even under a microscope. Unlike traditional scientific simulations that rely on physical equations, the Livermore project delved into the curious properties of quantum mechanics as they relate to electrons and subatomic forces. The project demonstrates the potential of supercomputers to explore proteins, new strains of semiconductors, and new nanotechnology materials whose behavior is largely directed by the complex and sporadic behavior of their electrons. Qbox, the software used in the simulation, was written by former Livermore researcher Francois Gygi. Qbox was written specifically for Blue Gene L, the Livermore supercomputer that consists of 131,000 processors. It took two years just to get the software to run on Blue Gene L, as the researchers had to coordinate the thousands of processors while working with 6,500 GB of data. "Startup to 'Liberate' Library Characterization" http://www.eetimes.com/showArticle.jhtml?articleID=190200038 Promising a ten-fold speedup in cell library characterization for nanometer ICs, startup Altos Design Automation Inc. this week is introducing itself and its first product, Liberate. It's a step towards Altos' long-term goal of generating statistical timing models. The Altos founders felt there was "gaping hole" in the market. The problem, Altos CEO Jim McCanny said, is that the libraries needed at 90 nm and below have a lot more "views." They use cells with multiple threshold voltages and dynamic voltage scaling, and even for nominal static timing analysis, designers must look at different voltage and temperature corners for these cells. Add in the process variations needed to support statistical analysis, and it may take 20 to 100 times longer to build a library. Altos promises to introduce a new generation of super-fast tools that will let designers characterize statistical libraries in about the same amount of time they currently spend characterizing nominal libraries. "Cooley Survey: Rare Details on DFM Tools, Xilinx Freebies Catchup up With Synplicity Tools, RTOSes, Catapult C, Fishtail, Sierra DA, etc" http://www.eetimes.com/showArticle.jhtml?articleID=189601468 A fresh "census report" John Cooley posted on Deepchip.com, surveyed in depth by EE Times, includes interviews with two users of ClearShape's InShape tool for DFM -- something that has never happened before. Several users claim that free FPGA design tools from Xilinx are largely on part with Synplicity tools, although Synplify Pro is receiving excellent reviews. A survey of Real-Time OSes analogizes WindRiver VxWorks with Microsoft Windows and Mentor's Nucleus with Linux. Mentor's Catapult C is receiving positive reviews from Japan and Europe, while a tape-out attributed to Sierra DA tools legitimizes them as viable competition in the market. "Concurrent Layout and Package Design for Deep Sub-micron ICs" http://www.chipdesignmag.com/display.php?articleId=446 emiconductor companies continue to offer an increasing amount of transistors dutifully following Moore's Law. Die sizes have grown to 20 x 20 mm and larger to provide useful silicon area. Given such opportunity, engineers can create entire systems on chip (SoC) offering an ever-growing inventory of functions packaged in products with decreasing dimensions. "The Looming Gap between Design Debugging and Results Analysis" http://www.chipdesignmag.com/display.php?articleId=447 Integrated circuit (IC) design size and complexity are increasing for all chips these days, and the impacts on yield and time-to-market are felt throughout EDA. For analog and mixed-mode chips, the increase in analog complexity and clock frequency conspire to further complicate the matter. Debug time is becoming a greater issue, and designers are faced with time pressures even as they have to more quickly compare more complex testbench data to idea/ post-layout simulation results. What can be done about this increased pressure? "Unisys Confirms Shift on Mainframe CPUs" http://www.computerworld.com/action/article.do?command=viewArticleBasic&taxonomyId=9&articleId=112281 Unisys Corp. last week said it plans to phase out the CMOS processors used in its ClearPath mainframes and enable its MCP and OS 2200 operating systems to run on Intel-based hardware. "Firm's Initiative Targets SystemC IP Interoperability" http://www.embedded.com/shared/printableArticle.jhtml?articleID=190301137 For designers working on complex system-on-chip (SoC) projects, heavy intellectual property (IP) reuse is a given. But while using third-party SystemC IP offers designers a welcomed shortcut, stitching the blocks together remains a complicated and time-consuming undertaken that can cost companies months. "Virtual Prototype Revived" http://www.eeproductcenter.com/embedded/brief/showArticle.jhtml?articleID=190301397 Silicon virtual prototyping (SVP) tools once promised to greatly accelerate ASIC design, but most of the original providers have disappeared. Diana Raggett, president and CEO of startup Javelin Design Automation, believes the time has come for a second generation and a fresh approach. "Startups Integrate ESL Synthesis, Power Estimation" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=190300737 EDA startups Sequence Design and Bluespec Inc. have entered into a partnership that aims to offer customers electronic system level (ESL) productivity combined with an ability to analyze architectures for performance, area and power, the companies said Thursday (July 6). "Is Chip Design Different After 90 nm?" http://www.edn.com/article/CA6347251.html?industryid=2284 Design teams find that success requires some fundamental changes in thinking and in team structure in the 90- and 65-nm processes. "Plain-Vanilla EDA Gets Its Due" http://www.eetasia.com/ARTICLES/2006JUN/C/2006JUN_EDNOTE_WK2.HTM These days, the excitement in EDA centers on electronic system-level tools and design-for-manufacturability. But unsolved problems remain in plain-vanilla synthesis, placement and routing. Three years ago, Jason Cong, professor of computer science at the University of California at Los Angeles, argued in a paper that contemporary IC placement algorithms leave so much wire length on the table that chip designs are essentially several technology generations behind where they should be. The "optimality gap" between actual and ideal placement results diverged by 1.46 to 2.38 times. "UMC Collaborating with EDA Startup on Statistical Timing" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=190300470 Silicon foundry United Microelectronics Corp. (UMC) and EDA startup Extreme DA Corp. have entered into a collaboration to provide sub-90-nanometer variation-aware IC design flows system-on-chips (SoCs), the companies said Thursday (July 6). "Power Reduction Tool Extends to 65-nm" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=190300222 Power-focused EDA startup Azuro Inc. has released version 3 of its PowerCentric low power clock implementation tool, which extends the company's power reduction capabilities to support advanced variability-aware design flows at 65-nanomter and below, Azuro said Wednesday (July 5). "The MathWorks Introduces Systems Biology Software" http://home.businesswire.com/portal/site/google/index.jsp?ndmViewId=news_vie w&newsId=20060626005073&newsLang=en The MathWorks today announced the introduction of SimBiology, the first graphical systems-biology tool that leverages an industry-proven mathematical engine to enable biologists to simulate, model, and analyze biochemical pathways in one integrated environment. Built on The MathWorks MATLAB(R) engine, SimBiology improves communication among modelers and biologists and eliminates the need for computational biologists to apply specific tools at each phase of systems biology. ======================================================================== Submission deadlines: --------------------- VLSI'07 - Int'l Conference on VLSI Design Bangalore, India Jan 6-10, 2007 Deadline: Jul 14, 2006 http://www.vlsiconference.com/2007/ ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies: Theory and Applications Cairo, Egypt Jan 3-6, 2007 Deadline: Jul 17, 2006 http://www.thetaconf.org/ ISLPED'06 - Int'l Low Power Design Contest Tegernsee, Germany Oct 4 - 6, 2006 Deadline: Jul 31, 2006 http://www.islped.org/contest.html DATE'07 - Design Automation and Test in Europe Nice, France Apr 16-20, 2007 Deadline: Sep 10, 2006 http://www.date-conference.com/ IP-SOC'06 - IP Based SoC Design Grenoble, France Dec 6-7, 2006 Deadline: Sep 25, 2006 http://www.us.design-reuse.com/ipsoc2006/ ISCAS'07 - Int'l Symposium on Circuits and Systems New Orleans, LA May 27-30, 2007 Deadline: Oct 6, 2006 http://www.iscas2007.org/ SPL'07 - Southern Conference on Programmable Logic Mar del Plata, Argentina Feb 26-28, 2007 Deadline: Oct 23, 2006 http://www.splconf.org/ NOCS'07 - Int'l Symposium on Networks-on-Chips Princeton, New Jersey May 7-9, 2007 Deadline: Dec 1, 2006 http://www.nocsymposium.org/ ======================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- DAC'06 - Design Automation Conference San Francisco, CA Jul 24-28, 2006 http://www.dac.com/ DAC'06 - SIGDA Ph.D. Forum at DAC San Francisco, CA Jul 25, 2006 http://www.sigda.org/daforum/ EUC'06 - Int'l Conference on Embedded And Ubiquitous Computing Seoul, Korea Aug 1-4, 2006 http://euc06.euc-conference.org/ MWSCAS'06 - Int'l Midwest Symposium on Circuits and Systems San Juan, Puerto Rico Aug 6-9, 2006 http://mwscas06.ece.uprm.edu/ EC'06 - Int'l Workshop on Embedded Computing Columbus, OH August 14, 2006 http://juliet.stfx.ca/~lyang/icpp06-ec/ ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 http://asap2006.grm.polymtl.ca/ ISOCC'06 - Int'l SoC Design Conference Seoul, Korea Oct 26-27, 2006 http://www.isocc.org/ ICCAD'06 - Int'l Conference on Computer-Aided Design San Jose, CA Nov 5-9, 2006 http://www.iccad.com/ PDCS'06 - Int'l Conference on Parallel and Distributed Computing and Systems Dallas, TX Nov 13-15, 2006 http://www.iasted.org/conferences/2006/Dallas/pdcs.htm ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies: Theory and Applications Cairo, Egypt Jan 3-6, 2007 http://www.thetaconf.org VLSI'07 - Int'l Conference on VLSI Design Bangalore, India Jan 6-10, 2007 http://www.vlsiconference.com/2007/ ASPDAC'07 - Asia and South Pacific Design Automation Conference Yokohama, Japan Jan 23-26, 2007 http://www.aspdac.com/aspdac2007/ ======================================================================== Upcoming funding opportunities ------------------------------- DOD Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA) Deadline: September 30, 2008 http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.ht ml Threat System Validation Support Deadline: July 10, 2006 http://fedbizopps.cos.com/cgi-bin/getRec?id=20060525a5 BAA for Simulation and Training Technology R&D Deadline: Continuous until December 31, 2010 http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451 Optoelectronics: Components and Information Processing Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/optoelectronics.htm Software and Systems Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/software_and_systems.htm Information Fusion and Artificial Intelligence Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/information_fusion.htm Computational Mathematics Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/computational_mathematics.htm Electronics Design for Cold Environments (CRREL-66) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf Sensors, Sensor Systems, Data Acquisition, Processing, and Transmission Systems (ITL-6) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf High Performance Computing (HPC) and Networking (ITL-4) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf NSF Instrument Development for Biological Research (IDBR) (NSF 06-570) Deadline: August 25, 2006 http://www.nsf.gov/pubs/2006/nsf06570/nsf06570.htm Operations Research (OR) Deadline: September 1, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13341&org=NSF&from=fund Information and Intelligent Systems: Advancing Human-Centered Computing, Information Integration and Informatics, and Robust Intelligence (NSF 06-572) Full Proposal Deadline(s): October 19, 2006 for Large Projects November 02, 2006 for Medium Projects December 06, 2006 for Small Projects http://www.nsf.gov/pubs/2006/nsf06572/nsf06572.htm Partnerships for Innovation (NSF 06-550) Letter of Intent Deadline Date: June 28, 2006 Full Proposal Deadline Date: August 30, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=5261&org=CISE&from=home DARPA TRUST for Integrated Circuits (BAA06-40) Original Response Date: Aug 11, 2006 http://www.darpa.mil/baa/baa06-40.html Cognitive Information Processing Technology (BAA02-21) Deadline: June 5, 2007 http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm Advanced Soldier Sensor Information System and Technology Deadline: August 04, 2006 http://fedbizopps.cos.com/cgi-bin/eps/spg/ODA/DARPA/CMO/BAA04-38/listing.htm l?notice=MOD NASA Applied Information Systems Research Deadline: January 30, 2007 http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&sol Id={0B64DB41-8F7D-C949-44CD-9D04A484B653}&path=open Fellowship Sloan Research Fellowships Deadline: September 15, 2006 http://www.sloan.org/programs/scitech_fellowships.shtml ======================================================================== Call For Papers ----------------------------- The 13th IEEE* International Symposium on Asynchronous Circuits and Systems http://conferences.computer.org/async2007/ The International Symposium on Asynchronous Circuits and Systems provides a high-quality forum for scientists and engineers to present their latest research findings. Authors are invited to submit full papers on all aspects of asynchronous design. Topics of interest include, but are not limited to: . Mixed synchronous/asynchronous architectures, interfaces, andcircuits. . High-speed/low-power asynchronous logic, memories, and interconnects. . High-level design and synthesis of self-timed circuits. . Physical design of unclocked logic and pipelines. . Formal methods for correctness and performance analysis of asynchronous designs. . Test, reliability, security, and radiation tolerance. . CAD for asynchronous design and validation. . Asynchronous System-on-Chip (SoC), System-in-Package (SiP), and Network-on-Chip (NoC). . Novel asynchronous architectures. . Asynchrony and latency tolerance in system-level design. Papers should be submitted via the conference web site. The submission should not exceed ten pages in IEEE double-column format. Papers that exceed the length limit may not be reviewed. Papers will be evaluated by the program committee and reviews will be based on scientific merit, innovation, relevance, and presentation. New-idea papers are encouraged, and the program committee recognizes that such papers may contain less evaluation than papers in established areas. Accepted papers will be published in an IEEE proceedings and distributed at the symposium. Please check the symposium website for up-to-date information: http://conferences.computer.org/async2007 Paper Schedule: * Submission deadline: September 25, 2006 * Notification of acceptance: November 20, 2006 * Final version due: December 20, 2006 General Chairs Peter Beerel, Univ. of Southern California Marly Roncken, Intel Program Chairs Mark Greenstreet, Univ. of British Columbia Montek Singh, U. of N. Carolina, Chapel Hill Publications Erik Brunvand, Univ. of Utah Best Paper Award H. Peter Hofstee, IBM Research Invited Speakers and Tutorials Jan Rabaey, Univ. Calif. Berkeley Ivan Sutherland, Sun Microsystems Publicity Ran Ginosar, Technion, Israel Industrial Liaisons Ken Stevens, Univ. of Utah Pascal Vivet, CEA-LETI, Grenoble Finance Peter Beerel, Univ. of Southern California Local Arrangements Jeff Rulifson, Sun Microsystems ======================================================================== Call For Participation ----------------------- The 2006 Federated Logic Conference Seattle, Washington, USA August 10 -- August 22, 2006 http://www.easychair.org/FLoC-06/ Early registration deadline: July 10, 2006. We are pleased to announce the fourth Federated Logic Conference (FLoC'06) to be held in Seattle, Washington, in August 2006, at the Seattle Sheraton (http://www.easychair.org/FLoC-06/floc-hotel.html). FLoC'06 promises to be the premier scientific meeting in computational logic in 2006. The following conferences will participate in FLoC'06: CAV Conference on Computer Aided Verification (Aug 17-20) ICLP Int'l Conference on Logic Programming (Aug 17-20) IJCAR Int'l Joint Conference on Automated Reasoning (Aug 17-20) LICS IEEE Symposium on Logic in Computer Science (Aug 12-15) RTA Conference on Rewriting Techniques and Applications (Aug 12-14) SAT Int'l Conference on Theory and Applications of Satisfiability Testing (Aug 12-15) The six major conferences will be accompanied by 41 workshops, held on Aug. 10-11, 15-16, and 21-22. The FLoC'06 program includes a keynote session to commemorate the Goedel Centenary, with John Dawson and Dana Scott as speakers, a keynote talk by David Harel, plenary talks by Randy Bryant and David Dill, and invited talks by F. Bacchus, A. Blass, B. Buchberger, A. Darwiche, M. Das, J. Esparza, J. Giesl, A. Gordon, T. Hoare, O. Kupferman, M. Lam, D. Miller, K. Sakallah, J. Stoy, and C. Welty. Seattle, the Emerald city, sits on the shores of Puget Sound surrounded by mountains to the east and west. Lovely views of blue waters and snow capped peaks seem to appear everywhere - around the next bend in the road or between the buildings downtown. Seattle is the gateway to the Pacific Northwest, a premier tourist attraction. In Seattle, Mt. Rainier enchants visitors; in Vancouver, British Columbia, the Coast Range juts out over downtown; and in Portland, 5,000 acres of forestland north of the city center harbor deer, elk, and the odd bear and cougar. Online registration for FLoC is now open at: http://www.easychair.org/FLoC-06/ Deadline for early registration is July 10, 2006. The rates agreed upon between FLoC and the Seattle Sheraton are very reasonable rates for a first-class hotel in downtown Seattle during the summer vacation season. To reduce conference costs and keep registration fees reasonable, FLoC is contractually obligated to meet a commitment for a certain number of FloC attendees staying in the conference hotel. FLoC attendees are strongly encouraged to use the Seattle Sheraton for conference accommodation. Deadline for preferred hotel rate is July 21, 2006. FLoC'06 Steering Committee Moshe Y. Vardi (General Chair) Thomas Ball (Conference Co-Chair) Jakob Rehof (Conference Co-Chair) Edmund Clarke (CAV) Reiner Hahnle (IJCAR) Manuel Hermenegildo (ICLP) Phokion Kolaitis (LICS) Henry Kautz (SAT) Aart Middeldorp (RTA) Andrei Voronkov (IJCAR) ======================================================================== Call For Nominations --------------------------- 2006 ACM Outstanding Ph.D. Dissertation Award in EDA http://www.sigda.org/opda.html Submission Deadline: Aug 15, 2006 Award Description: Design automation has gained widespread acceptance by the VLSI circuits and systems design community. Advancement in computer-aided design (CAD) methodologies, algorithms, and tools has become increasingly important to cope with the rapidly growing design complexity, higher performance requirements, and shorter time-to-market demands. To encourage innovative, ground-breaking research in the area of electronic design automation, the ACM's Special Interest Group on Design Automation (SIGDA) has established an ACM award to be given each year to an outstanding Ph.D. dissertation that makes the most substantial contribution to the theory and/or application in the field of electronic design automation. The award consists of a certificate and a check for $1,000 and will be presented at the 2006 International Conference on Computer Aided Design in San Jose, California. The award will be selected by a committee of experts from academia and industry in the field and appointed by ACM in consultation with the SIGDA Chair. Nomination Requirements and Procedure: * Each department of any university may nominate at most one Ph.D. dissertation whose final submission date is between July 1, 2005 and June 30, 2006. * Each nomination package must be postmarked by Aug. 15 and should consist of: 1. Five copies of the dissertation 2. A statement from the nominee, up to three pages in length, which explains the significance and major contributions of the work 3. A nomination letter from nominee's department chair or dean of the school endorsing the application 4. Up to three additional letters of recommendation from experts in the field. These letters may be included in the package or sent separately to the address below. Item 1 must be submitted in (preferably bound) hard copy form. Other items may be submitted as paper printouts or electronically. All the nomination materials should be mailed to: Prof. Radu Marculescu Attn: ACM Outstanding Ph.D. Dissertation Award in EDA Carnegie Mellon University Department of Electrical & Computer Engineering 5000 Forbes Ave. Pittsburgh, PA 15213-3890 Tel: (412) 268-8710 Fax: (412) 268-3204 Email: radum@ece.cmu.edu ======================================================================== Call For Nominations ------------------------ 2006 SIGDA Outstanding New Faculty Award Deadline: August 15, 2006 SUMMARY The SIGDA Outstanding New Faculty Award recognizes a junior faculty member early in her or his academic career who demonstrates outstanding potential as an educator and/or researcher in the field of electronic design automation. While prior research and/or teaching accomplishments are important, the selection committee will especially consider the impact that the candidate has had on her or his department and on the EDA field during the initial years of their academic appointment. The award is presented annually at ICCAD, and currently consists of a $1,000 award to the faculty member, along with a citation. ELIGIBILITY Outstanding new faculty who are developing academic careers in areas in or related to electronic design automation are encouraged to apply for this award. Note that this award is not intended for senior or highly experienced investigators who have already established independent research careers, even if they are new to academia. Candidates must have recently completed at least one full academic year and no more than four full academic years in a tenure-track position. Applications will also be considered from people whose appointments are continuing (non-visiting) positions with substantial educational responsibilities regardless whether or not they are tenure track. Persons holding research-only positions are not eligible. Exceptions to the timing requirements will be made for persons who have interrupted their academic careers for substantive reasons, such as family or medical leave. The presence of such reasons must be attested by the sponsoring institution, but no explanation is needed. APPLICATION Candidates applying for the award must submit the following to the selection committee no later than August 15, 2006: (1) a 2-page statement summarizing the candidate's teaching and research accomplishments since beginning their current academic position, as well as an indication of plans for further development over the next five years; (2) a copy of a current curriculum vitae; (3) a letter from either the candidate's department chair or dean endorsing the application. Application packets (preferably as email attachments in pdf) should be sent to: Professor Martin D.F. Wong University of Illinois at Urbana-Champaign Department of Electrical and Computer Engineering 1308 W. Main St., 409 CSL Urbana, IL 61801 email: mdfwong@uiuc.edu phone: 217-244-1729 fax: 217-244-1946 ======================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. First time users will be required to choose a password.) ======================================================================== Notice to Authors By submitting your contributions to ACM SIGDA, you acknowledge that they contain only your own work (minor edits by others are allowed) and are not subject to third-party licenses and copyrights. The contents of the ACM SIGDA newsletters are released by SIGDA into Public Domain, except when explicitly noted otherwise. SIGDA newsletters are routinely reproduced on the SIGDA Web site and the ACM Digital Library, may be reproduced in printed publications and appear on the Wikipedia Web site --- without express notice and royalties. If you wish to restrict the distribution of your work or retain copyright for your contribution, please contact the editors. Last revised by I. Markov - 05/21/06 ========================================================================