======================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org ======================================================================== 1 April 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 7 Online archive: http://www.sigda.org/newsletter ======================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What is Rent's Rule? Contributing author: Dirk Stroobandt, Ghent University, Belgium Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Upcoming Funding Opportunities Qinru Qiu (6) Call for Papers: International Conference on Computer-Aided Design (ICCAD) Kathy MacLennan (7) Call for Papers: 9th International Conference on Information Technology (CIT 2006) Saraju Mohanty ======================================================================== Dear ACM/SIGDA members, We would like to inlucde a short notice that the submission deadline to the 2nd NANOARCH workshop is extended to: Abstract: March 29; Full paper: April 5. Contributed by: Jie Chen, . As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; ======================================================================== SIGDA News ----------------------- "Performance no longer driving node migrations, de Geus says" http://www.eetimes.com/showArticle.jhtml?articleID=183701067 Accordng to Synopsys Chairman and CEO Aart de Geus, migration to the 65-nanometer node and beyond is spurred by the desire to integrate more functionality in system-on-chips and decrease power consumption, rather than to shorten clock cycles. He described this as a major departure from the way that the semiconductor industry has operated throughout its history --- migrating to more advanced technology nodes to improve performance and keep on pace with Moore's Law. Over the last few years, de Geus suggested, chip makers have concluded that, while they could improve a device's speed through technology shrink, it is not economically feasible. Raw speed, he said, can be improved through other means, such as employing multiple cores. "Cray breaks 1 TB/sec barrier for CPU to CPU communication" http://www.marketwire.com/mw/release_html_b1?release_id=109968 Sandia's 10,350-processor Red Storm is the first computer to exceed 1 TB/sec on the HPCC benchmark test. Red Storm posted 1.8 TB/sec on the PTRANS interconnect bandwidth test that is part of the High Performance Computing Challenge (HPCC) test suite. By comparison, this figure represents 40 times more communications power per teraflop than the PTRANS result posted by an IBM Blue Gene system that has more than 10 times as many processors. "Nanoelectronics roadmap aims to speed commercialization" http://www.eetimes.com/showArticle.jhtml?articleID=183701368 The IEEE launched an Nanoelectronics Standards Roadmap initiative on Marfh 21, aiming to move nanoelectronics innovations from laboratory to the marketplace for applications ranging from communications, information technology, consumer products and optoelectronics. The roadmap builds on similar efforts targeting carbon nanotube technology. The 2003 effort yielded several standards activities, including the recently approved IEEE 1650, "Standard Test Methods for Measurement of Electrical Properties of Carbon Nanotubes." "VLSI lists top equipment vendors in '05" http://www.eetimes.com/showArticle.jhtml?articleID=183701645 Applied Materials Inc. remained the world's largest chip-equipment vendor with $6.234 billion in sales in 2005, according to VLSI Research. Applied was followed by Tokyo Electron Ltd. ($4.455 billion), ASML Holding NV ($3.16 billion), KLA-Tencor ($2.005 billion), Advantest Corp. ($1.96 billion), Nikon Corp. ($1.566 billion), Lam Research Corp. ($1.382 billion), Novellus Systems Corp. ($1.302 billion), Hitachi High-Technologies Corp. ($1.277 billion), and Canon Inc. ($1.247 billion). The share of Japasnese suppliers (5 out of top 10) grew to 43% at the expense of U.S. suppliers (44%, 2% down), while Europe's share, represented by ASML, gew from 12% to 13%. "Sun releases open-source processor" http://www.eetimes.com/showArticle.jhtml?articleID=183701660 Sun Microsystems announced the release of open-source hardware and software specifications for its multi-threaded UltraSparc T1 (Niagara) processor, now called OpenSparc T1. It is a 64-bit 32-thread processor design free of any royalty or licensing fees. An RTL description in Verilog is available the OpenSparc web site (http://opensparc.sunsource.net/nonav/index.html along with a verification suite and simulation models, an instruction set architecture specification, and the Solaris 10 operating system simulation images. "Gartner's Foundry Rankings for 2005" http://www.eetimes.com/showArticle.jhtml?articleID=183702841 Gartner Dataquest Inc. published rankings of top foundries in the world, based on their market shares and sales. As expected, Taiwan's TSMC and UMC lead the pack with 44.8% and 15.4%. China's SMIC (6.4%) outran Singapore's Chartered (6.2%), and IBM remained in the fifth place with 4.5%. Also in top ten are (not in order) MagnaChip and Dongbu from South Korea, Taiwan's Vanguard, China.s Shanghai Hua Hong NEC. U.S.-based Jazz Semiconductor, at the 10th place, captured 1.1% of the worldwide market. "IBM Explores Atomic-Level Computing" http://www.toptechnews.com/news/IBM-Explores-Atomic-Level-Computing/story.xhtml?story_id=13300DOSR62Q The tools are now in place to do additional atomic-scale research that could lead to breakthroughs in data storage on desktop devices," said Andreas Heinrich of IBM's Almaden Research Center in San Jose, California. "It may be possible to supersede Moore's Law, although it will require more experimentation using tight controls. "Physicist expects radical change" http://www.mlive.com/features/aanews/index.ssf?/base/features-1/1141918926128650.xml&coll=2 The computer revolution that took off after World War II got its zip from astounding feats that continue to produce ever smaller, more powerful computer chips. In the next 20 years, when computer chips likely will shrink to the size of a molecule, the usual way of computing will hit a wall, says University of Michigan physicist Chris Monroe. At that tiny scale, the strange forces of quantum mechanics will confound normal processing, necessitating a new way of computing. "Synplicity to Focus On FPGA and Verification Markets" http://www.tmcnet.com/usubmit/2006/03/30/1521701.htm Synplicity, Inc. (Nasdaq:SYNP), a leading supplier of software for the design and verification of semiconductors, today announced a plan to re-focus its R&D investment and headcount on its strategic growth opportunities in FPGA implementation and ASIC verification. "IBM Researchers Build First Nanotube Integrated Circuit" http://www.hpcwire.com/hpc/608327.html IBM has announced that its researchers have built the first complete electronic integrated circuit around a single "carbon nanotube" molecule, a new material that shows promise for providing enhanced performance over today's standard silicon semiconductors. The achievement is significant because the circuit was built using standard semiconductor processes and used a single molecule as the base for all components in the circuit, rather than linking together individually-constructed components. This can simplify manufacturing and provide the consistency needed to more thoroughly test and adjust the material for use in these applications. "Startup switches to assembly language development environment" http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=184417448 In a surprise move, Bluespec, developer of the only ESL synthesis toolset for control logic and complex datapaths in chip design, announced today that it has abandoned high-level software languages for its internal development of tools and has switched, instead, to assembly language. "Synopsys Rolls Out Full SystemVerilog Support" http://www.reed-electronics.com/electronicnews/article/CA6317145.html?industryid=21370 Design and verification engineers who use Synopsys Inc.'s design and verifcation tools can now benefit from the faster performance, improved productivity and increased predictability advantages of the IEEE SystemVerilog standard as the Mountain View, Calif.-based EDA supplier said today it now supports the language in all of its design and verification products. "EDA Providers Crack Down on Software Piracy" http://www.reed-electronics.com/article/CA6321050.html Following a successful settlement of illegal use of its software, Mentor Graphics and the EDA industry are sending a message to software pirates that their activities will not go unnoticed or unpunished. "EDA Vendors Roll Out 65nm DFM Support for IBM-Chartered-Samsung Partnership" http://www.reed-electronics.com/electronicnews/article/CA6320376.html?industryid=21370 Fulfilling its plan announced in September 2005 to implement an end-to-end DFM flow optimized across the Common Platform partnership, Chartered Semiconductor Manufacturing, IBM Corp. and Samsung Electronics Co. Ltd. today announced the first set of deliverables. "A CEO at the Heart of Tech" http://money.cnn.com/2006/03/31/technology/fastforward_fortune/ NEW YORK (FORTUNE) - Aart de Geus is one of the most insightful people I know in the technology industry, so I was happy to sit down for lunch with him this week. De Geus is CEO and co-founder of Synopsys (Research), a company that sits at the intersection of just about every trend there is. "Preserving Japanese EDA Development" http://neasia.nikkeibp.com/neasia/003815 "We had to do something while there were still some EDA development engineers left in Japan," said Shin'ichi Ishibashi, first chairman of the Japan EDA Venture Consortium (JEVeC) of Japan. JEVeC was formally established on January 23, 2006, following preparations by Ishibashi, becoming the first electronic design automation (EDA) vendor's association created in Japan. Ishibashi is also the president and chief executive office (CEO) of EDA vendor Jedat Inc of Japan. "Scientists demonstrate quantum nature of entanglement swapping" http://www.physorg.com/news63037231.html As if plain old quantum entanglement weren.t strange enough for modern physics, now physicists are entangling already entangled particles. In entanglement swapping, one particle of an entangled pair becomes entangled with a third particle, which itself becomes entangled with the other particle in the first pair, even though the two never interact. Here.s how physicists are unraveling this behavior and manipulating it for use in quantum communications and high-speed computing. "Memory architectures evolve to support handset design" http://pd.pennnet.com/articles/Article_Display.cfm?ARTICLE_ID=249574&p=21 Cell phones are the latest and most demanding development platform, where the desire for mobile, high-speed data-for music, video, and now even mobile TV-runs head on into the need for reasonable battery life. Nowhere is this conflict more keenly felt than in the memory arena, where tradeoffs and complex architectures are the order of the day while DRAM, SRAM, and flash manufacturers scramble to develop low-power products to retain their cell phone sockets. Almost all of the growth in the memory market is coming from the portable segment. "Sub-32nm Lithography Race" http://neasia.nikkeibp.com/neasia/003819 For the past three decades semiconductor industry pundits have been predicting the end of optical lithography. But recent developments in laboratories throughout the world indicate that optical lithography's life can continue to be extended, and that the technology may be here to stay. "From UML to embedded system: Is it possible?" http://www.embedded.com/shared/printableArticle.jhtml?articleID=183702862 Software design tools have been around for over 20 years now. Although they have improved greatly over that time, there seems to be a problem with generated code: it is still too inefficient and unreadable. Until now. "CoWare offer virtual testing of embedded software" http://www.electronicsweekly.com/Articles/Article.aspx?liArticleID=38092&PrinterFriendly=true EDA company CoWare has announced new tools that enable designers to develop and test embedded software, from device drivers up to application software, on a virtual hardware system. "DFM Support for 65nm Announced" http://www.eetimes.com/showArticle.jhtml?articleID=184416983 Three semiconductor companies calling themselves Common Platform manufacturing partners (IBM Microelectronics, Chartered Semiconductor and Samsung) announced the availability of design-for-manufacturing (DFM) technology, models, design kits and data files from EDA and DFM suppliers in support of the companies' joint 65-nanometer manufacturing process. According to the Common Platform companies, the capabilities and support available through this DFM initiative provide additional functionality for verification of manufacturability and drive greater manufacturing awareness earlier in the design process. "Alcatel and Lucent Technologies announce Merger" http://www.eetimes.com/showArticle.jhtml?articleID=183702422 Telecoms equipment companies Alcatel and Lucent Technologies said Sunday they had entered a definitive agreement to merge and form a new group with revenues of around $25.4 billion. The transaction, which will see Alcatel shareholders have the lion's share of the new company, stands to create a world leader in its sector and comes amid a wave of consolidation in the telecoms industry. ======================================================================== What is Rent's Rule? --------------------------------- Dirk Stroobandt Ghent University, Belgium In the 1960's, E.F. Rent, an IBM employee, found a remarkable trend between the number of pins (terminals T) at the boundaries of IBM IC designs and the number of internal components (blocks B). On a log-log plot, these datapoints were on a straight line, implying a power-law relation T = t B^p where t and p are constants. Rent never published his findings (except through an internal memorandum within IBM) but the relation was described in 1971 by Landman and Russo [1]. They performed a hierarchical circuit partitioning in such a way that at each hierarchical level (top-down) the least number of interconnections had to be cut to partition the circuit (in more or less equal parts). At each partitioning step, they noted the number of terminals and the number of blocks in each partition and then partitioned the sub-partitions further. They found the power law rule applied to the resulting T versus B plot and named it "Rent's rule". Christie and Stroobandt [2] later derived Rent's rule theoretically for homogeneous systems and pointed out that the amount of optimization achieved in placement is reflected by the parameter p, the "Rent exponent", which also depends on the circuit topology. In particular, values p<1 correspond to a greater fraction of short interconnects. The constant t in Rent's rule can be viewed as the average number of terminals required by a single logic block since T = t when B = 1. Random arrangement of logic blocks typically have p=1. Larger values are impossible since the maximum number of terminals for any region containing B logic blocks in a homogeneous system is given by T = t B. Lower bounds on p depend on the interconnection topology since it is generally impossible to make all wires short. This lower bound p* is often called the "intrinsic Rent exponent", a notion first introduced in [3]. It can be used to characterize optimal placements and also measure the interconnection complexity of a circuit. Higher (intrinsic) Rent exponent values correspond to a higher topological complexity. One extreme example (p=0) is a long chain of logic blocks, while a clique has p=1. In realistic 2D circuits, p* ranges from 0.5 for highly-regular circuits (such as SRAM) to 0.75 for random logic [4]. To estimate Rent's exponent, one can use top-down partitioning, as used in min-cut placement. For every partition, count the number of terminals connected to the partition and compare it to the number of logic blocks in the partition. Rent's exponent can then be found by fitting these datapoints on a log-log plot, resulting in an exponent p'. For optimally partitioned circuits, p' = p* but this is no longer the case for practical (heuristic) partitioning approaches. For partitioning-based placement algorithms p* <= p' <= p [5]. Landman and Russo found a deviation of Rent's rule near the "far end", i.e., for partitions with a large number of blocks, which is known as "Region II" of Rent's Rule [1]. A similar deviation exists at for small partitions, and has been found by Stroobandt [6] who called it Region III. Another IBM employee, Donath, discovered that Rent's rule can be used to estimate the average wirelength and the wirelength distribution in VLSI chips [8,9]. This motivated the System Level Interconnect Prediction workshop, founded in 1999, and an entire community working on wire length prediction (see a survey in [7]). The resulting wirelength estimates have been improved significantly since then and are now used for "technology exploration" [10]. The use of Rent's rule allows to perform such estimates /a priori/ (i.e., before actual placement) and thus predict the properties of future technologies (clock frequencies, number of routing layers needed, area, power) based on limited information about future circuits and technologies. A comprehensive overview of work based on Rent's rule can be found in [11] and [7]. [1] B. S. Landman and R. L. Russo, On a Pin Versus Block Relationship For Partitions of Logic Graphs, IEEE Trans. on Comput., col. C-20, pp. 1469-1479, 1971. [2] P. Christie and D. Stroobandt, The Interpretation and Application of Rent's Rule, IEEE Trans. on VLSI Systems, Special Issue on System-Level Interconnect Prediction, vol. 8, no. 6, pp. 639-648, 2000. [3] L. Hagen, A. B. Kahng, F. J. Kurdahi and C. Ramachandran, On the Intrinsic Rent Parameter and Spectra-based Partitioning Methodologies, IEEE Trans. on Comput.-Aided Des., Integrated Circuits \& Syst., vol. 13, no. 1, pages 27 - 37, 1994. [4] R. L. Russo, On the Tradeoff Between Logic Performance and Circuit-to-Pin Ratio for LSI, IEEE Trans. Comput., vol. C - 21, pages 147 - 153, 1972. [5] P. Verplaetse, J. Dambre, D. Stroobandt, and J. Van Campenhout, On Partitioning vs. Placement Rent Properties, Intl. Workshop on System-Level Interconnect Prediction (SLIP 2001), pp. 33 - 40, March 2001. [6] D. Stroobandt, On an efficient method for estimating the interconnection complexity of designs and on the existence of region III in Rent's rule, Proc. 9th Great Lakes Symposium on VLSI, pp. 330 - 331, 1999. [7] D. Stroobandt, A Priori Wire Length Estimates for Digital Design. Kluwer Academic Publishers. ISBN 0-7923-7360-X. 2001. pp. 298. [8] W. E. Donath, Placement and Average Interconnection Lengths of Computer Logic, IEEE Trans. Circuits & Syst., vol. CAS-26, pp. 272 - 277, 1979. [9] W. E. Donath, Wire Length Distribution for Placements of Computer Logic, IBM J. of Research and Development, vol. 25, pp. 152 - 155, 1981. [10] A. E. Caldwell, Y. Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. L. Markov, M. Oliver, D. Stroobandt, and D. Sylvester, GTX: The MARCO GSRC Technology Extrapolation System, IEEE/ACM Design Automation Conf., pp. 693 - 698, June 2000. [11] D. Stroobandt, Recent Advances in System-Level Interconnect Prediction, IEEE Circuits and Systems Society Newsletter, vol. 11, no. 4, pages 1; 4-20; 48, December 2000. Invited. Available at http://www.nd.edu/~stjoseph/newscas/. ======================================================================== Submission deadlines: --------------------- SBCCI'06 - Symposium on Integrated Circuits and Systems Design Ouro Preto, Minas Gerais, Brazil Aug 28-Sep 1, 2006 Deadline: Apr 2, 2006 http://www.sbc.org.br/sbcci FDL'06 - Forum on specification & Design Languages TU Darmstadt, Germany Sep 19-22, 2006 Deadline: Apr 3, 2006 http://www.ecsi-association.org/ecsi/fdl/fdl05/default.htm TACS'06 - Workshop on Temperature Aware Computer Systems Boston, MA Jun 18, 2006 Deadline: Apr 7, 2006 http://www.eecs.harvard.edu/~dbrooks/tacs06/index.html APCCAS'06 - Asia Pacific Conference on Circuits and Systems Grand Copthorne Waterfront, Singapore Dec 4-7, 2006 Deadline: Apr 15, 2006 http://www.apccas.org/ ICCAD'06 - Int'l Conference on Computer Aided Design San Jose, CA Nov 5-9, 2006 Deadline: Apr 19, 2006 http://www.iccad.com/ HiPC'06 - Int'l Conference on High Performance Computing Bangalore, India Dec 18-21, 2006 Deadline: May 5, 2006 http://www.hipc.org/ CODES-ISSS'06 - Int'l Conference on Hardware/Software Codesign and System Synthesis Seoul, Korea Oct 22-25, 2006 Deadline: May 8, 2006 http://www.codes-isss.org/ ICFPT'06 - Int'l Conference on Field-Programmable Technology Bangkok, Thailand Dec 13-15, 2006 Deadline: Jun 12, 2006 http://www.icfpt2006.org/ ======================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- ISPD'06 - Int'l Symposium on Physical Design San Jose, CA Apr 9-12, 2006 http://www.ispd.cc/ VLSI-TSA'06 - Int'l Symposium on VLSI Tech., Sys. & Applications VLSI-DAT'06 - Int'l Symposium on VLSI Design, Automation & Test Hsinchu, Taiwan Apr 24-26, 2006 http://vlsidat.itri.org.tw/2006/General/ IPDPS'06 - Int'l Parallel and Distributed Processing Symposium Rhodes Island, Greece Apr 25-29, 2006 http://www.ipdps.org/ GLSVLSI'06 - Great Lakes Symposium on VLSI Philadelphia, PA Apr 30-May 2, 2006 http://www.glsvlsi.org/ ISCAS'06 - Int'l Symposium on Circuits and Systems Island of Kos, Greece May 21-24, 2006 http://www.iscas06.org/ ETS'06 - European Test Symposium Southampton, UK May 21-25, 2006 http://www.ecs.soton.ac.uk/~mz/ETS06/ ICSE'06 - Int'l Conference on Software Engineering Shanghai, China May 20-28, 2006 http://www.icse-conferences.org/2006/ DAC'06 - Design Automation Conference San Francisco, CA Jul 24-28, 2006 http://www.dac.com/ DAC'06 - SIGDA Ph.D. Forum at DAC San Francisco, CA Jul 25, 2006 http://www.sigda.org/daforum/ ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 http://asap2006.grm.polymtl.ca/ ======================================================================== Upcoming funding opportunities ------------------------------- DOD Optoelectronics: Components and Information Processing Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/optoelectronics.htm Software and Systems Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/software_and_systems.htm Information Fusion and Artificial Intelligence Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/information_fusion.htm Computational Mathematics Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/computational_mathematics.htm Electronics Design for Cold Environments (CRREL-66) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf Sensors, Sensor Systems, Data Acquisition, Processing, and Transmission Systems (ITL-6) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf High Performance Computing (HPC) and Networking (ITL-4) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf NSF Computing Community Consortium (CCC): Defining the Large-Scale Infrastructure Needs of the Computing Research Community - NSF 06-551 Deadline: June 10, 2006 http://www.nsf.gov/pubs/2006/nsf06551/nsf06551.htm Theoretical Foundations 2006 (TF06) . NSF 06-542 Deadline: May 25, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13679&org=CISE&from=home Information and Intelligent Systems: Advancing Collaborative and Intelligent Systems and their Societal Implications - NSF 05-551 Deadline: April 18, 2006; April 20, 2006 http://www.nsf.gov/publications/pub_summ.jsp?ods_key=nsf05551 DARPA Advanced Soldier Sensor Information System and Technology Deadline: August 04, 2006 http://fedbizopps.cos.com/cgi-bin/eps/spg/ODA/DARPA/CMO/BAA04-38/listing.html?notice=MOD Fellowship Sloan Research Fellowships Deadline: September 15, 2006 http://www.sloan.org/programs/scitech_fellowships.shtml ======================================================================== Call for Papers ------------------------ 2006 International Confernece on Computer-Aided Design (ICCAD) ICCAD serves EDA & Design professionals, highlighting new challenges and innovative solutions for Integrated-Circuit Design Technologies and Systems AREAS OF INTEREST AUTHOR INFORMATION AND FORMAT In addition to traditional CAD topics, ICCAD has expanded its focus to include innovative design technologies for devices, circuits, and systems in both CMOS and non-CMOS technologies. Original technical submissions focusing on, but not limited to, the following topics are invited: 1) PHYSICAL DESIGN AND TEST 1.1 High-Level physical design and synthesis. Estimation and hierarchy management. Partitioning, floorplanning and global placement. Detailed and incremental placement. 1.2 Routing and detailed physical design. Detailed routing, post-placement layout and optimization. Clock network design. 1.3 Design and CAD for analog, RF, and mixed signal. Mixed technology design (thermal, packaging, micro-mechanical). 1.4 Testing. Fault modeling, delay test, analog and mixed signal test. Fault simulation. ATPG. BIST and DFT. Memory test and repair. Core, system, and MEMS test. Power issues in Test. Test data compression. 2) SYNTHESIS AND SYSTEM DESIGN 2.1 Logic synthesis. Interaction between physical design and logic synthesis. Technology mapping. Synthesis for FPGAs. Asynchronous circuit design. Optimization for area, timing, power, and yield. Design for manufacturability and robustness. 2.2 High-Level synthesis. Refinement techniques. Direct compilation and post-optimization. Physically aware techniques for early exploration. Micro-architectural transformations. Protocol and interface design for correctness. Memory system synthesis. 2.3 System synthesis. HW and SW co-optimization and co-exploration. Multi-processor systems (heterogeneous, homogeneous, reconfigurable). On-chip communication optimization. HW/SW platforms. Compilation and code generation techniques. 2.4 Embedded and programmable systems. Real-time software and RTOS. Reuse techniques. Rapid system prototyping. Methodologies and case studies. 3) VERIFICATION, MODELING AND SIMULATION 3.1 Interconnect parameter extraction. Circuit simulation and circuit model generation. 3.2 Signal integrity analysis. Reliability and thermal analysis. Yield and EMC/EMI simulation techniques. 3.3 Gate, switch, and circuit level timing and power analysis. Power/Ground network analysis and optimization. LVS. 3.4 Formal verification techniques. HW/SW co-simulation. Switch, logic and behavioral simulation, and design validation. Software verification. Emulation. 4) INNOVATIVE DESIGN TECHNOLOGIES FOR SYSTEMS, CIRCUITS AND DEVICES 4.1 Trends and perspectives in system-level design, with emphasis on power, software, performance and configurability: SoC, SiP, programmable and reconfigurable platforms. 4.2 Novel circuit and system implementation styles: new circuit families, fault- and variations-tolerant circuits, FPGAs, programmable fabrics, and structured ASICs. 4.3 Novel ideas in layout and physical implementation: manufacturable layout, 3-D integration, packaging and package analysis. 4.4 Alternative technologies. Modeling, simulation, analysis and design methods for novel device structures: nanotechnology, MEMS, quantum, molecular and bioelectronics. Proposals for Panel Sessions and (Embedded) Tutorials are also invited. Panel suggestions should describe the topic and should list suggested participants. Tutorial suggestions should focus on the state-of-the art in a specific area. Both half-day and full-day tutorial suggestions are welcome. Embedded tutorials (1.5-2 hours) should address emerging fields. All tutorial proposals should list the presenters. PAPER SUBMISSION GUIDELINES All submissions must be made electronically at the ICCAD web site (www.ICCAD.com) before 5:00 pm Mountain Daylight Time (GMT - 07:00), April 19, 2006. Papers will not be accepted for submission after 5:00 pm MDT. This is a firm deadline and no exceptions will be made. Regular paper submissions must (1) be in PDF format only, (2) be no more than 8 pages (including the abstract, figures, tables, and references), double columned, 9pt or 10pt font, and (3) must not include name(s) or affiliation(s) of the author(s) anywhere on the manuscript, abstract, or bibliographic citations. Submissions not adhering to these rules, or those previously published or simultaneously submitted to another conference will be rejected. Additional submission guidelines are available on the ICCAD web site after March 15, 2006. Format templates are available on the ICCAD web site for your convenience, but are not required. All regular papers will be reviewed as finished papers; preliminary submissions will be at a disadvantage. Authors of accepted papers must sign a copyright release form for their paper. Notice of acceptance will be sent via email by June 20, 2006. NOTE: In the proceedings, four pages are free of charge and each page beyond four pages is charged $125.00 per page. ICCAD Home Page: http://www.iccad.com Author's Schedule Deadline for submissions: 5:00 pm MDT (GMT - 07:00) April 19, 2006 Notification of acceptance: June 20, 2006 Deadline for final version submission: 5:00 pm MDT, August 8, 2006 Strict paper submission deadline : April 19, 2006, 5:00 PM Mountain Daylight Time. One or more outstanding submissions will be recognized with the IEEE/ACM William J. McCalla ICCAD Best Paper Award. Please direct all correspondence to: ICCAD Publications Department MP Associates, Inc. 5405 Spine Rd., Ste. 102 Boulder, CO 80301 Telephone: 303-530-4562 Fax: 303-530-4334 Email: iccadpapers@mpassociates.com Conference dates: November 5-9, 2006 GENERAL CHAIR Soha Hassoun Tufts University soha@cs.tufts.edu PROGRAM CHAIR Georges Gielen Katholieke University Leuven georges.gielen@esat.kuleuven.be PROGRAM VICE CHAIR Sani Nassif IBM Corp. nassif@us.ibm.com ======================================================================== CALL FOR PAPERS -------------------------- 9th International Conference on Information Technology (CIT 2006) 18th-21st December 2006, Bhubaneswar, India. http://www.citconference.org Jointly Organized by Orissa Information Technology Society (http://www.oits.org ) and Institute of Technical Education and Research, Bhubaneswar, India (http://www.iterindia.com ). Co-sponsored by IEEE North Jersey Section. Conference Proceedings to be Published by IEEE-CS (http://www.computer.org) press. CIT (Conference on Information Technology) is a premier international conference and forum for high quality research in the area of Information Technology. CIT2006 is being jointly organized by the Orissa Information Technology Society (http://www.oits.org) and the Institute of Technical Education and Research, Bhubaneswar, India (http://www.iterindia.com/) to be held at Bhubaneswar, India from 18th-21st December 2006. Researchers, developers, and practitioners from academia and industry are invited to present their research findings on various topics related to Information Technology and its Applications. Four types of submissions are solicited: regular papers, short papers, poster papers and tutorials. All accepted papers after peer-review will be published by IEEE-CS (http://www.computer.org) press. CONFERENCE WEBSITE: http://www.citconference.org/ or http://www.cs.unt.edu/~smohanty/CIT2006/ CONFERENCE TRACKS: CIT encourages submissions in all the areas of information technology. However, the papers in the following 6 tracks will be primary focus of this year conference (CIT2006). The submissions in each track could be on any of the topics listed, but are not limited to them. (1) Bioinformatics and Computational Biology: Novel applications in Bioinformatics, Data Mining and Statistical Modeling of biological data, Visualization of Biological Processes and Data, Management, Migration and Integration of Biological Databases, Biological Database search, indexing and access. (2) Communication Networks and Protocols: Broadband Multimedia Communications, Wireless Ad hoc/ Sensor Networks, Network Security, Wireless and Mobile Communications, Emerging Information Technology Networks. (3) Language Processing: Character recognition, text to speech conversion, speech synthesis, Signal and Image Processing. (4) Security, Content Protection, and Digital Rights Management: Watermarking, Steganography, Cryptography, Biometrics, Digital Libraries. (5) Databases, Information Warehousing and Data Mining: Intelligent Databases, Query and Constraint-based Data Mining, Mining Spatial and Temporal Data, Mining of Data Streams, Feature Extraction, Collaborative filtering/ personalization, Cost-based Decision making, Visual Data Mining, Privacy Sensitive Data Mining. (6) Application Specific Software and Hardware Systems: Embedded Information Systems, Hardware/Software/Firmware issues, Nano-technology and Applications, Quantum Information Processing. PAPER SUBMISSION: Papers offering high quality original and unpublished research, case studies and implementations are solicited for this conference. The papers need to be submitted online through the conference website indicated above. Three types of papers of papers will be considered: regular papers (6-pages), short papers (4-pages), poster papers (2-pages). All submitted papers will undergo DOUBLE-blind- review by a strong team of reviewers and program committee members consisting of leading researchers around the globe. Authors need to prevent identity disclosure in many ways: (1) by not listing names and affiliations of the authors on the manuscript, (2) by not saying "my work" or "our work" in the text while citing self references, and (3) by not writing acknowledgments such a way that identity of authors are implied. Author information should ONLY be included in the submission form. All accepted papers will be printed in the conference proceedings provided that at least one author registers for the conference. BEST PAPER AWARDS: Three awards will be conferred with due recommendations from the program committee from the papers presented in the conference. Each award will carry cash prize and citation. Amiya K. Pujari Award is provided for the Best Paper of the conference. Narayan Misra Award is given to the best paper from Orissa. One student best paper award will be awarded from the papers with students as the leading authors. FELLOWSHIPS: The Steering Committee will award limited number of fellowships to students based on need and merit, to partially cover expenses of attendees from India. Applications must be submitted before the fellowship application deadline using the conference website. IMPORTANT DATES: Papers and tutorials submission deadline: 15th June 2006 Notifications of review status (Acceptance or Declination): 15th August 2006 Camera ready copies of accepted papers or tutorial-abstracts due: 15th September 2006 COMMITTEE: General Chairs D. Mishra, New Jersey Institute of Technology, USA, dmisra@njit.edu. B. K. Sarap, Institute of Technical Education and Research, Bhubaneswar, India, b_sarap@yahoo.co.in. Program Chairs S. P. Mohanty, University of North Texas, USA, smohanty@cs.unt.edu. A. Sahoo, Indian Institute of Technology, Bombay, India, sahoo@it.iitb.ac.in. Steering Committee Chair C. Baral, Arizona State University, USA, chitta@asu.edu. Tutorial Chair A. G. Ramakrishnan, Indian Institute of Science, Bangalore, India, ramkiag@ee.iisc.ernet.in. P. Behera, Utkal University, Bhubaneswar, India, p_behera@hotmail.com. Publicity Chair P. Guturu, University of North Texas, USA, guturu@unt.edu M. Satapathy, Abo Akademi University, Finland, nuapatana@gmail.com. R. Mohanty, Institute of Technical Education and Research, Bhubaneswar, India, 2rkm@email.com. Organizing Chairs M. Mishra, Institute of Technical Education and Research, Bhubaneswar, India, manoj_oec@sify.com. A. K. Das, Center for IT Education, Bhubaneswar, India, ajitmita@yahoo.co.in. Finance Chair A. K. Nayak, Silicon Institute of Technology, Bhubaneswar, India, ajit@silicon.ac.in. M. Mallick, Institute of Technical Education and Research, Bhubaneswar, India. Advisory Chair S. Padhy, Utkal University, Bhubaneswar, India, spadhy04@yahoo.co.in. Members of Program Committee A strong team of leading researchers around the globe, a complete list is available in the website. ======================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. 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