======================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org ======================================================================== 15 March 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 6 Online archive: http://www.sigda.org/newsletter ======================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) What are Nonvolatile Memories? Contributing author: Erwin J. Prinz, Freescale Semiconductor Inc. Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Upcoming Funding Opportunities Qinru Qiu (6) Call for Papers: IEEE Design & Test January-February 2007 Special Issue on Biochips Krishnendu Chakrabarty (7) Call for Papers: The 2006 IEEE International Conference on Field-Programmable Technology (ICFPT 06) Theerayod Wiangtong ======================================================================== Dear ACM/SIGDA members, As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; ======================================================================== SIGDA News ----------------------- "Bush Signs Bill Targeting Knock-offs" http://www.eetimes.com/showArticle.jhtml?articleID=183700579 The "Stop Counterfeiting In Manufactured Goods" bill closes loopholes that allowed the shipment of fake products (from electronic components and automotive parts to apparel) into the US --- a problem that cost manufacturers an estimated $200B a year. The bill also requires courts to order the destruction of all counterfeit products seized as part of a criminal investigation. Those convicted of counterfeiting must reimburse the legitimate businesses they exploited. A number of manufacturers in consumer goods and retail industries are looking at embedding radio frequency identification (RFID) tags in individual items as an option to stop counterfeiting. "PlayStation launch may be delayed" http://news.bbc.co.uk/1/hi/business/4731128.stm Sony's next-generation PlayStation 3 console may not be available this Spring as planned, but rather delayed until the Fall. The new PlayStation will have faster processors and sharper graphics, but disagreements on industry-wide specifications (not defined by Sony) are apparently responsible for delaying the commercial launch and denting Sony shares. "ATI, Nvidia back TSMC 80-nm 'half-node' process" http://www.eetimes.com/showArticle.jhtml?articleID=177100620 TSMC has started manufacturing circuits using an 80-nanometer .half-node. process. Fabless graphics chip companies ATI Technologies Inc. and Nvidia Corp. have both indicated backing for the technology, which promises performance gains and chip-size reductions by up to 19%, compared to the more common 90nm technology node. In the past, TSMC has offered such half-shrinks from 0.35um to 0.30um, from 0.25um to 0.22um, from 0.18um to 0.16um and from 0.13um to 0.11um. "Research Illuminates How Electrons Behave on Various Surfaces" http://www.azonano.com/news.asp?newsID=1978 Hrvoje Petek, University of Pittsburgh professor of physics and codirector of Pitt's Gertrude E. and John M. Petersen Institute of NanoScience and Engineering (PINSE), has published two papers in recent weeks that literally illuminate how electrons behave on various surfaces. "Unified Data Model Critical to Addressing Sub-Nanometer DFM/DFY Issues" http://www.chipdesignmag.com/display.php?articleId=352 IC manufacturers face costly design iterations if they do not address design for manufacturing (DFM) or design for yield (DFY) concerns prior to tapeout. With mask costs exceeding $1 million for advanced processes, additional changes to a design mean significantly increased direct costs to any device that a manufacturer wishes to take to market. Even worse, long delivery delays that accompany design iterations can reduce market share and revenue as product life cycles shrink in today's competitive environment. "The economics of structured- and standard-cell-ASIC designs" http://www.edn.com/article/CA6313388.html?spacedesc=features Although structured ASICs promise a shorter schedule than standard-cell ASICs, this abbreviation comes at a price. Structured ASICs are more expensive on a per-unit basis, allow less customization, and offer lower performance than standard-cell ASICs. For various designs, customers often have to choose from standard-cell ASICs, structured ASICs, and FPGAs. "Using softcore-based FPGAs to balance hardware/software needs in a multicore design" http://www.embedded.com/shared/printableArticle.jhtml?articleID=181502570 Embedded system design is a dance between software and hardware. The question is, which of the two gets to call the tune? Who leads? Who controls the relationship? "Securing pervasively connected embedded MCUs" http://www.embedded.com/shared/printableArticle.jhtml?articleID=165701128 One of the defining characteristics of the new pervasively connected computing environment is that it is still in a state of definition. Two steady states -- computing and networking -- have converged and the result is not a third steady state but a still chaotic one. "Beyond Silicon" http://www.technologyreview.com/InfoTech-Hardware/wtr_16594,294,p1.html Last week, at the semiannual Intel Developer Forum in San Francisco, chip-maker Intel announced a transistor made from a material called indium antimonide (InSb) that had some impressive stats: it was clocked at 1.5 times the speed of silicon-based transistors and used one-tenth the power. "Researchers simulate complete structure of virus.on computer" http://www.physorg.com/news11746.html When Boeing and Airbus developed their latest aircraft, the companies. engineers designed and tested them on a computer long before the planes were built. Biologists are catching on. They.ve just completed the first computer simulation of an entire life form . a virus. "New nanotechnology process may improve RAM memories and the storage capacity of hard drives" http://nanotechwire.com/news.asp?nid=2980 A team of scientists from the Universitat Aut?noma de Barcelona, in collaboration with colleagues from the Argonne National Laboratory (USA) and the Spintec laboratory (Grenoble, France), has for the first time produced microscopic magnetic states, known as "displaced vortex states", that will allow an increase in the size of MRAMs (which are not deleted when the computer is switched off). The research has been published in Physical Review Letters and Applied Physics Letters. "Computing with light?" http://www.hpcwire.com/hpc/581079.html Light is the solution. It's also the problem. That's the paradox HP Labs' Quantum Information Processing Group is beginning to unravel with its research into optical quantum computing. The group has been investigating ways to use photons, or light particles, for information processing, rather than the electrons used in digital electronic computers today. Their work holds promise for someday developing faster, more powerful and more secure computer networks. "System architects get help from emulators" http://www.edn.com/article/CA6313386.html?industryid=2815 Emulators, which designers once used only for debugging at the last stages of design implementation and for regression testing, are now becoming useful tools for system architects, as well. "Structuring the future of custom devices" http://www.cieonline.co.uk/cie2/articlen.asp?pid=&id=8677 Structured ASICs are a new class of product that needs a new class of design tool. Behrooz Zahiri, director of product marketing at Magma Design Automation, looks at the different types of structured ASIC technologies and how to optimise the tool flow to get the best results. "C to FPGA: Putting theory into practice" http://www.cieonline.co.uk/cie2/articlen.asp?pid=&id=7544 C-based synthesis is to custom programmable hardware what software compilation is to the general purpose processor. Celoxica's general manager Jeff Jussel takes C to system-level FPGA design. "EDA industry urged to stick to standards" http://www.electronicsweekly.com/Articles/2006/03/16/37943/EDAindustryurgedtosticktostandards.htm An argument bubbled to the surface during the DATE design software exhibition last week over whose responsibility it is to improve the state of the fractured design tool chain. Rene Penning de Vries, chief technology officer of Philips Semiconductors, told delegates in his keynote address that he was fed up with having to integrate the hundreds of EDA tools a large integrated device manufacturer (IDM) uses and wanted the industry to sort things out. "EDA Startup Aims at Concurrent Timing, SI and Yield Analysis" http://www.reed-electronics.com/electronicnews/article/CA6315487.html A new EDA company called Athena Design Systems Inc. wants to bring concurrent extraction, timing and signal analysis to the IC physical design flow. "Tanner EDA - Analog and mixed-signal chip design gets more productive" http://www.electropages.com/viewArticle.aspx?intArticle=6652 The new S-Edit design environment for schematic capture has been introduced by Tanner EDA, a specialist provider of cost-effective and easy-to-use tools for the design of mixed-signal and analog circuits. For the first time, users can get an integrated suite of affordable Tanner analog and mixed-signal design capture, simulation, layout, design rule checking and verification tools. S-Edit also supports legacy tools and data to preserve existing investments, says the company. "Slack EDA-market growth doesn't portend chip trends" http://www.edn.com/article/CA6313384.html?industryid=2284 A less-than-stellar record of recent growth in the EDA industry has been a hot topic. Clearly, such trends matter greatly to the companies that sell EDA tools. But, too often, observers relate tough times in the EDA market to potential softness in the semiconductor business. That link is tenuous at best. In fact, a recent DesignCon panel that set out to discuss stagnant EDA growth ended up pointing out just how big the separation between EDA and the semiconductor industry can be. "Mask prices flatten but tool costs soar" http://www.eetimes.com/showArticle.jhtml?articleID=181503925 For years, the semiconductor industry has worried about the soaring costs of photomasks. Today, there is good and bad news for merchant photomask makers - and their customers. Photomask prices have not increased as fast as some had predicted, but capital and tool costs continue to escalate at an alarming rate. Still, the initial price for an early-version, leading-edge "mask-set" is projected to jump from $1 million at the 90-nm node to $1.5 million at the 65-nm node. "Simucad releases compact Spice models" http://www.eetimes.com/showArticle.jhtml?articleID=181504116 Simucad Design Automation Inc., a privately held EDA vendor announced the availability of LDMOS and HV MOS compact Spice models for its SmartSpice analog simulator and SmartSpiceRF harmonic-based simulator. LDMOS (lateral double diffuse metal oxide semiconductor) is based on the Philips LDMOS compact model, a specialized model for high-voltage and RF applications developed by Philips Research Labs in Eindhoven, the Netherlands. HV MOS compact model is based on the popular BSIM3 from the University of California-Berkeley. ======================================================================== What are Nonvolatile Memories? ------------------------------ Erwin J. Prinz, Ph.D., Freescale Semiconductor Inc. In nonvolatile memories the stored information is retained when they are powered off. In a PC, this function is performed by the hard drive, but there are many applications not suited to hard drives due to size or environmental constraints, such as heat and vibration. In these applications, silicon technology based nonvolatile memories are employed. Silicon-based nonvolatile memories are fabricated as stand-alone components, or embedded into systems on a chip. Within each technology node, the largest memory, or the largest die area, which can be manufactured at acceptable yields, is usually reserved for stand-alone memories. Smaller memories can be economically embedded with a CPU and peripherals to form microcontrollers. Other embedded applications include field programmable gate arrays, smart cards, RF ID's, etc. The ideal "universal" memory has the density (stored bits per area) of a DRAM, the fast access time of an SRAM, and is nonvolatile with unlimited number of write/erase cycles (endurance) and fast write/erase times. But, until this memory is invented, trade-offs have to be made, depending on the application. In classical nonvolatile memories, the first tradeoff is to allow the write and erase times to be much slower than the read times. For example, in a byte-erasable EEPROM ("electrically erasable / programmable read only memory") write times are in the 1-10 msec range, while read times can be 10-100 nsec. Byte erasability requires a large area per bitcell, so the next tradeoff is to limit erasability to blocks of, e.g., 1-100 kB while employing a smaller area for each bitcell. This memory is called a "Flash EEPROM" (byte-programmable, block erasable). Within Flash EEPROMs, the next tradeoff is between (random access) read access time and density. In many data storage applications, random access to arbitrary bytes is not needed, and can be replaced by parallel access to "pages" of information, read in parallel. An architecture well suited to slow, but parallel access is the "NAND" Flash, in which contacts within the array are only made to strings of, e.g., 32 bitcells, rather than to each bitcell, thereby saving valuable bitcell area. Within the industry, NAND Flash is driving the growth in the stand-alone memory market due the explosive growth in mobile data storage applications such as MP3 players and digital cameras. In systems where Flash memory is used to store code for an on-board CPU, and where this code is executed while reading from the Flash memory as opposed to first transferring the code into an on-board SRAM, random access from the Flash memory is mandatory to prevent the need for "wait states". For this application, the "NOR" architecture is usually employed, in which within the array of bitcells, contacts are inserted next to each bitcell. This results in a faster, lower resistance, read path, and therefore faster random access time, at the expense of die area. Prominent examples for code storage nonvolatile memory applications are cellular phones and automotive engine and transmission controllers. In the classical silicon-based nonvolatile memories, information is stored by inserting and/or removing charge into one or more storage sites located in the gate oxide of a MOSFET, thereby changing its threshold voltage. In most nonvolatile memories, the storage site is a piece of silicon surrounded by a silicon dioxide insulator, forming a "floating gate". In other memories (named "SONOS"), charge is stored in the electron and hole traps of a nitride layer, sandwiched between two silicon dioxide layers. Recently, charge storage in silicon nanocrystals has also been explored. Within the industry it is believed that the paradigm of storing information by changing a MOSFET threshold voltage by charge insertion into the gate oxide can be extended from the currently used 90nm technology node through less than 30nm feature sizes. It is likely that over time floating gates will be replaced by charge storage in thin films of nitride or nanocrystals, as the voltage on a floating gate is affected (disturbed) by all elements in its neighborhood capacitively coupled to it. With the huge financial success of the established silicon-based nonvolatile memories and the absence of a "universal" memory, great effort is spent within the industrial and academic community to increase the understanding of the existing technology, all the way from the system level through memory design to the individual parts of the bitcell. For both existing and new memory approaches, statistical reliability models for all observed mechanisms of data loss are needed before a product can be committed to the most demanding applications such as automotive engine control where more than 20 years of data retention are required and zero failures are a must. Thorough reliability evaluations are being conducted on thousands of parts before committing to productization. Apart from furthering the understanding of the mainstream technology, alternative, more universal, memory concepts are being developed. Examples are ferroelectric capacitors (FeRAM), magnetic tunnel junctions (MRAM), and phase change-induced resistance change in a chalcogenide film (PRAM or OUM). While all of these memories are built in a 2-dimensional layer of bitcells, attempts are also made to build memory cells in 3 dimensions, by stacking several layers of bitcells above the decode circuitry on the silicon wafer surface. For these alternative memory concepts to be applied in high volume, they have to be capable of replacing existing approaches at the leading technology node, or they have to enable new applications due to their different set of properties within the tradeoffs described above, just as the NOR Flash enabled code storage in the cellular phone, leading the strong nonvolatile memory market growth. To learn more, see: 1. General Overview: W. D. Brown, J. E. Brewer, "Nonvolatile Semiconductor Memory Technology," IEEE Press, ISBN 0-7803-1173-6. 2. Floating Gate Scaling: ftp://download.intel.com/technology/silicon/Stefan%20IMST%20092804.pdf 3. Nanocrystal Charge Storage: http://www.freescale.com/webapp/sps/site/overview.jsp?nodeId=0ST28747134 4. MRAM: http://www.freescale.com/webapp/sps/site/overview.jsp?nodeId=0ST287482186253 5. Phase Change Memory: http://www.ovonyx.com/ovonyxtech.html 6. 3-Dimensional Integration of Nonvolatile Memory: http://www.matrixsemi.com/technology/scientific-literature.html ======================================================================== Submission deadlines: --------------------- ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 Deadline : March 20, 2006 http://asap2006.grm.polymtl.ca/ PACT'06 - Int'l Conference on Parallel Architectures and Compilation Techniques Seattle, WA Sep 16-20, 2006 Deadline: Mar 27, 2006 http://www.pactconf.org VLSI-SoC'06 - Int'l Conference on Very Large Scale Integration French Riviera, France Oct 16-18, 2006 Deadline: Mar 27, 2006 http://tima.imag.fr/conferences/VLSI-SoC06/ SBCCI'06 - Symposium on Integrated Circuits and Systems Design Ouro Preto, Minas Gerais, Brazil Aug 28-Sep 1, 2006 Deadline: Apr 2, 2006 http://www.sbc.org.br/sbcci FDL'06 - Forum on specification & Design Languages TU Darmstadt, Germany Sep 19-22, 2006 Deadline: Apr 3, 2006 http://www.ecsi-association.org/ecsi/fdl/fdl05/default.htm ICCAD'06 - Int'l Conference on Computer Aided Design San Jose, CA Nov 5-9, 2006 Deadline: Apr 19, 2006 http://www.iccad.com/ HiPC'06 - Int'l Conference on High Performance Computing Bangalore, India Dec 18-21, 2006 Deadline: May 5, 2006 http://www.hipc.org/ CODES-ISSS'06 - Int'l Conference on Hardware/Software Codesign and System Synthesis Seoul, Korea Oct 22-25, 2006 Deadline: May 8, 2006 http://www.codes-isss.org/ ICFPT'06 - Int'l Conference on Field-Programmable Technology Bangkok, Thailand Dec 13-15, 2006 Deadline: Jun 12, 2006 http://www.icfpt2006.org/ ======================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- ISQED'06 - Int'l Symposium on Quality Electronic Design San Jose, CA Mar 27-29, 2006 http://www.isqed.org/ SASIMI'06 - Workshop on Synthesis and System Integration of Mixed Information Technology Nagoya, Japan Apr 3-4, 2006 http://www.sasimi.jp/ ISPD'06 - Int'l Symposium on Physical Design San Jose, CA Apr 9-12, 2006 http://www.ispd.cc/ VLSI-TSA'06 - Int'l Symposium on VLSI Tech., Sys. & Applications VLSI-DAT'06 - Int'l Symposium on VLSI Design, Automation & Test Hsinchu, Taiwan Apr 24-26, 2006 http://vlsidat.itri.org.tw/2006/General/ IPDPS'06 - Int'l Parallel and Distributed Processing Symposium Rhodes Island, Greece Apr 25-29, 2006 http://www.ipdps.org/ GLSVLSI'06 - Great Lakes Symposium on VLSI Philadelphia, PA Apr 30-May 2, 2006 http://www.glsvlsi.org/ ISCAS'06 - Int'l Symposium on Circuits and Systems Island of Kos, Greece May 21-24, 2006 http://www.iscas06.org/ ETS'06 - European Test Symposium Southampton, UK May 21-25, 2006 http://www.ecs.soton.ac.uk/~mz/ETS06/ ICSE'06 - Int'l Conference on Software Engineering Shanghai, China May 20-28, 2006 http://www.icse-conferences.org/2006/ DAC'06 - Design Automation Conference San Francisco, CA Jul 24-28, 2006 http://www.dac.com/ DAC'06 - SIGDA Ph.D. Forum at DAC San Francisco, CA Jul 25, 2006 http://www.sigda.org/daforum/ ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 http://asap2006.grm.polymtl.ca/ ======================================================================== Upcoming funding opportunities ------------------------------- DOD Optoelectronics: Components and Information Processing Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/optoelectronics.htm Software and Systems Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/software_and_systems.htm Information Fusion and Artificial Intelligence Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/information_fusion.htm Computational Mathematics Deadline: Continuous http://www.afosr.af.mil/ResearchPrograms/computational_mathematics.htm Electronics Design for Cold Environments (CRREL-66) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf Sensors, Sensor Systems, Data Acquisition, Processing, and Transmission Systems (ITL-6) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf High Performance Computing (HPC) and Networking (ITL-4) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf NSF Theoretical Foundations 2006 (TF06) Deadline: May 25, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13679&org=CISE&from=home Integrative Graduate Education and Research Traineeship Program . NSF 06-525 Deadline: March 27, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=12759&org=CISE&from=home Information and Intelligent Systems: Advancing Collaborative and Intelligent Systems and their Societal Implications - NSF 05-551 Deadline: April 18, 2006; April 20, 2006 http://www.nsf.gov/publications/pub_summ.jsp?ods_key=nsf05551 DARPA Spoken Language Communication and Translation System for Tactical Use (TRANSTAC) Deadline: March 24, 2006 (Initial Closing) http://www.darpa.mil/ipto/solicitations/open/06-21_PIP.htm Advanced Soldier Sensor Information System and Technology Deadline: August 04, 2006 http://fedbizopps.cos.com/cgi-bin/eps/spg/ODA/DARPA/CMO/BAA04-38/listing.html?notice=MOD NAVSEA Science and Technology BAA - Countermeasures Technology Deadline: Open until March 21, 2006 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Science and Technology BAA . Audition and Communication Deadline: Open until March 21, 2006 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Science and Technology BAA . Test and Evaluation Deadline: Open until March 21, 2006 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Fellowship NASA Summer Faculty Research Opportunities (NSFRO) Deadline: March 14, 2006; May 02, 2006 http://www.asee.org/resources/fellowships/nsfro/general.cfm Sloan Research Fellowships Deadline: September 15, 2006 http://www.sloan.org/programs/scitech_fellowships.shtml ======================================================================== Call For Papers ------------------- IEEE Design & Test January-February 2007 Special Issue on Biochips Guest Editors: Krishnendu Chakrabarty, Duke University (krish@ee.duke.edu), and Roland Thewes, Infineon Technologies (roland.thewes@infineon.com) IEEE Design & Test seeks original manuscripts for a special issue on Biochips, scheduled for January- February 2007. Biochips and biosensors are becoming increasingly popular for DNA analysis, clinical diagnostics, and detection and manipulation of bio-molecules. Biosensor systems automate highly repetitive laboratory tasks by replacing cumbersome equipment with miniaturized and integrated devices, and they enable the handling of small amounts (for example, nanoliters) of fluids. Thus, they are able to provide ultra detection at significantly lower costs per assay than traditional methods. The 2003 International Technology Roadmap for Semiconductors (ITRS) clearly identifies the integration of electrochemical and electrobiological techniques as one of the system-level design challenges that the industry will face beyond 2009. Efforts are underway in the electronics design automation community to identify synergies between biochipsand microelectronics CAD. The 2005 Design, Automation, and Test in Europe (DATE) conference included a well-attended .Biochips Day. event. A special session on bioMEMS took place at the 2004 IEEE/ACM Design Automation Conference. The 2005 IEEE/ACM/IFIP International Conference on Hardware-Software Co-design and System Synthesis (CODES-ISSS) included a special session on biochips and bioinformatics. The IEEE Transactions on CAD published a special issue on microfluidics-based biochips in February 2006. The 2006 DATE conference will co-host a workshop on biochips CAD. D&T.s special issue on biochips will focus on design, integration, and test issues related to biochips. Topics of interest include (but are not limited to) - design of microarrays (DNA and protein arrays); - microfludics-based biochips (electrowetting, electrokinetics, dielectrophoresis, and other actuation mechanisms); - magnetic biosensors; - design automation methods (simulation, synthesis, and layout); - test techniques (fault modeling, fault diagnosis, and reconfiguration). Industrial experiences and case studies are especially welcome. To submit a manuscript, please access Manuscript Central, http://cs-ieee.manuscriptcentral.com, and select Special Issue on Biochips. If you wish to participate as a reviewer, please contact dt-ma@computer.org. The submissions schedule is as follows: - 15 May 2006: Deadline for manuscript submissions. - 15 August 2006: Authors notified of acceptance with requested revisions. - 9 October 2006: Final copy due to dt-ma@computer.org. Acceptable file formats include MS Word, ASCII or plain text, PDF, and PostScript. Manuscripts should not exceed 5,000 words (with each averagesize figure counting as 150 words toward this limit), including references and biographies; this amounts to about 4,200 words of text and five figures. Manuscripts must be doubled-spaced, on A4 or 8.5-by-11 inch pages, and type size must be at least 11 points. Please include all figures and tables, as well as a cover page with author contact information (name, postal address, phone, fax, and e-mail address) and a 150-word abstract. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere, and all manuscripts must be cleared for publication. Accepted articles will be edited for structure, style, clarity, and readability. Please read IEEE Design & Test author guidelines at http://www.computer.org/dt/author.htm. ======================================================================== Call for Papers ----------------------- The 2006 IEEE International Conference on Field-Programmable Technology (ICFPT 06) ----------------------------------------- www.icfpt2006.org Fortune Hotel, Bangkok, Thailand December 13 - 15, 2006 Organized by the Mahanakorn University of Technology, Bangkok, Thailand Technical co-sponsorship by IEEE Circuit and Systems Society, Thailand Chapter ------------------------------------------------- CALL FOR PAPERS ================== ICFPT is a fast growing conference on field-programmable technologies, including complex programmable logic devices and systems containing such components. The development of, and the applications of, field-programmable technology have become an important topic of research for universities, government, and industry worldwide. Field-programmable devices combine the flexibility of software with the performance of hardware. Their regular structure facilitates rapid improvement in density, capability and speed. Field-programmable systems have a wide variety of applications, such as accelerating computations in molecular biology and medical imaging, low-power control and data processing for palm-size computers, and emulating novel electronic products before manufacture; even advanced microprocessors from Intel and ARM have benefited from field-programmable hardware emulators. Submissions are solicited on a wide variety of topics related to field-programmable technologies, including but not limited to: * Applications of field-programmable technology: biomedical and scientific computation accelerators, network processors, real-time systems, rapid prototyping, hardware emulation, digital signal processing, interactive multimedia, machine vision, computer graphics, cryptography, robotics, manufacturing systems, embedded applications, evolvable and biologically-inspired hardware. * Design techniques and tools for field-programmable technology: placement, routing, synthesis, verification, technology mapping, partitioning, parallelization, timing optimization, design and run-time environments, languages and modeling techniques, provably-correct development, intellectual property core based design, domain-specific development, hardware/software co-design. * Architectures for field-programmable technology: field programmable gate arrays, complex programmable logic devices, field programmable interconnect, field programmable analogue arrays, field programmable arithmetic arrays, memory architectures, interface technologies, low-power techniques, adaptive devices, reconfigurable computing systems, other emerging technologies. * Device technology for field-programmable logic: programmable memories including non-volatile, dynamic and static memory cells and arrays, interconnect devices, circuits and switches, emerging VLSI device technologies. * Novel use of reconfigurability, including evolvable hardware and adaptive computing, possible forms and system implications of reconfiguration for fault tolerance and avoidance, implications and effects of nanotechnology and reconfigurable computing and others. Important Dates: ================ Submission of papers: June 12 2006 Notification of acceptance: July 31 2006 Registration deadline: September 4 2006 Conference start: December 13 2006 Submission Guidelines ===================== The program committee solicits papers describing original research in field-programmable technology, including, but not limited to, the areas of interest indicated above. Papers should be submitted electronically in PDF format, following the IEEE style. Full papers should not exceed 8 pages in length, while posters should not exceed 4 pages in length. Manuscripts must not identify authors or their affiliations. Papers that identify authors will NOT be considered. Submissions must be made via the conference webs. The paper submission site for the conference is: http://www.icfpt2006.org/submit.htm Proposals for half and full day tutorials in the areas of interest are also sought. Initial inquiries should be directed to icfpt@icfpt2006.org. Questions regarding the FPT conference, including the submission procedure and grants, can be sent to: icfpt@icfpt2006.org Programme Committee: ==================== Alex Yakovlev (University of Newcastle, UK) Andre DeHon (Caltech, USA) Andy Ye (Ryerson University, Canada) Apostolos Dollas (Technical University of Crete, Greece) Christos-Savvas Bouganis (Imperial College, UK) David Kearney (University of South Australia, Australia) David Wu (Chinese University of Hong Kong) Dinesh Bhatia (University of Texas Dallas, USA) Eduardo Boemo (University of Madrid, Spain) Florent De Dinechin (ENS-Lyon, France) George Constantinides (Imperial College, UK) Gordon Brebner (Xilinx) Guy Lemieux (University of British Columbia, Canada) Henry Styles (Xilinx) Jim Hwang (Xilinx) Jinian Bian (Tsinghua University, China) Joao Cardoso (University of Algarve, Portugal) Jonathan Rose (Toronto University, Canada) Juanjo Noguera (Xilinx) Jürgen Teich (University of Erlangen-Nuernberg, Germany) Kara Poon (Actel) Katherine Compton (University of Wisconsin-Madison, USA) Kia Bazargan (University of Minnesota) Kobchai Dejhan (KMITL, Thailand) Koji Kotani (University of Tohoku, Japan) Laurence Turner (University of Calgary, Canada) Makoto Ikeda (University of Tokyo, Japan) Manfred Glesner (TU Darmstadt, Germany) Marco Platzner (University of Paderborn, Germany) Mark Shand (Hewlett Packard) Masahiro Fujita (University of Tokyo, Japan) Mike Hutton (Altera) Neil Bergmann (University of Queensland, Australia) Nikil Dutt (University of California Irvine, USA) Oliver Diessel (University of New South Wales, Australia) Oskar Mencer (Imperial College London, UK) Patrick Lysaght (Xilinx) Paul Beckett (RMIT University, Australia) Pedro Diniz (Information Sciences Institute, USA) Peter Cheung (Imperial College, UK) Phil James-Roxby (Xilinx) Philip Leong (Imperial College, UK) Ranga Vemuri (University of Cincinnati, USA) Ranjani Parthasarathy (Anna University, India) Roger Woods (Queen's University Belfast, UK) Russ Tessier (University of Massachusetts Amherst, USA) Sakir Sezer (Queen's University Belfast, UK) Satnam Singh (Microsoft) Satoshi Komatsu (University of Tokyo, Japan) Steve Wilton (University of British Columbia, Canada) Steven Quigley (University of Birmingham, UK) Tarek El-Ghazawi (George Washington University, USA) Tetsuo Hironaka (University of Hiroshima, Japan) Ting-Chi Wang (Tsing Hua University, Taiwan) Tom Kean (Algotronix) Tulika Mitra (NUS, Singapore) Vaughn Betz (Altera) Wai-Kei Mak (Tsing Hua University, Taiwan) Wanchalerm Pora (Chulalongkorn University, Thailand) Wayne Luk (Imperial College London, UK) Weng Fai Wong (NUS, Singapore) Yao-Wen Chang (National Taiwan University, Taiwan) Organizing Committee: ===================== General Chair: Sujate Jantarang (MUT) Vice Chair: Phaophak Sirisuk (MUT) Technical Program Co-Chairs: George Constantinides (Imperial College) Wai-Kei Mak (Tsing Hua University, Taiwan) Publications Chair: Nalin Sidahao (MUT) Exhibition Co-Chair: Jitkasame Ngarmnil (MUT) Apinunt Thanachayanont (KMITL) Publicity Co-Chair: Surin Kittitorakul (KMITL) Pinit Kumhom (KMUTT) Nattha Jindapetch (PSU) Local Arrangement Co-Chair: Peerapol Yuvapoositanon (MUT) Supakorn Siddichai (NECTEC) Review Process Administrator: Altaf Abdul Gaffar (Imperial College) Finance Chair and General Secretariat: Theerayod Wiangtong (MUT) ======================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. 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