======================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org ======================================================================== 15 February 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 4 Online archive: http://www.sigda.org/newsletter ======================================================================== Contents of this E-NEWSLETTER: (1) SIGDA News Contributing author: Tony Givargis Contributing author: Michael Orshansky Contributing author: Marc Riedel Contributing author: Igor Markov (2) "What is an And-Inverter Graph?" Contributing author: Alan Mishchenko Igor Markov (3) Paper Submission Deadlines Hai Zhou (4) Upcoming Conferences and Symposia Hai Zhou (5) Upcoming Funding Opportunities Qinru Qiu (6) Call for Nominations for Advanced Member Grades In the ACM Diana Marculescu (7) Call for Papers: 2nd IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH'2006) Steve Levitan Jie Chen ======================================================================== Dear ACM/SIGDA members, As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Igor Markov and Qing Wu, E-Newsletter Editors; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; Tony Givargis, E-Newsletter Associate Editor; Michael Orshansky, E-Newsletter Associate Editor; Marc Riedel, E-Newsletter Associate Editor; ======================================================================== SIGDA News ----------------------- "'Disruptive events' could change EDA landscape, panelists say" EE Times, 02/08/2006, Dylan McGrath http://www.eetimes.com/showArticle.jhtml?articleID=179101762 A panel of EDA insiders at DesignCon 2006 in Santa Clara debated the near future of the EDA industry in view of several "disruptive events" that may reshape the landscape. Gary Smith, chief EDA analyst at Garter Dataquest, expects new companies to emerge and substantial acquisitions to take place, including mergers between significant companies of equal size. He also likened the shift to electronic system level (ESL) tools to the shift that occurred in the 1980s, when a move to register-transfer level (RTL) methodologies resulted in a new set of EDA leaders. Jim Hogan, a VC investment insider, predicted a new wave of startup innovation by small companies that formed when the economy began to improve in 2003. He suggested that one of "disruptive events" will occur in the placer-and-route flow. Jim Kupec, chief operating officer at eSilicon Corp., pointed out that the number of ASIC design starts has relatively stabilized in the past three years, after a steady decline in 1999 through 2002. "ARM offers first clockless processor core" EE Times, Peter Clarke, 02/08/2006 http://www.eetimes.com/showArticle.jhtml?articleID=179101800 ARM Holdings plc and Handshake Solutions NV, a Royal Philips Electronics subsidiary, have developed an asynchronous processor based on the ARM9 core. The ARM996HS is marketed for automotive and medical applications. The lack of clock circuitry significantly reduce power consumption and extends battery life. Another advantage is low electromagnetic signature due to relatively low switching activity. The ARM996HS processor can be used in both synchronous and asynchronous system-on-chip designs, ARM said. The lack of clock-edge driven current peaks should enable easier integration with analog components, in mixed-signal SOCs. "TI, MIT claim lowest voltage SRAM" EE Times, Mark LaPedus, 02/08/2006 http://www.eetimes.com/showArticle.jhtml?articleID=179101614 An MIT paper at ISSCC describes an ultra-low-power, 256-kilobit SRAM based on TI.s 65-nm process technology and partially funded by DARPA. Using ultra-dynamic voltage scaling techniques . reportedly pioneered by MIT . the 0.4-volt, sub-threshold SRAM achieves 2.25 times lower leakage power, as compared to its six-transistor counterpart at 0.6 volts, according to TI and MIT. The SRAM also claims to incorporate 10 transistors per bitcell to enable operations down to 400-mV. Key innovations in this work include a new transistor design and the integration of analog power switches on the chip. "IBM to ISSCC: Give frequency its due" http://www.eetimes.com/showArticle.jhtml?articleID=179103424 In an age of multithreaded multicores, is frequency irrelevant? Intel seemed to answer in the affirmative when it announced a "right-hand turn" in architectural philosophy five years ago. But in a Power microprocessor being readied for a line of servers, IBM makes a case for pushing performance by pushing frequency. A new Power6 process from IBM featured a clock frequency of 4-5GHz, and used a variety of new circuit-level techniques to control power consumption. Higher frequency increase performance but also leads to power increases. "Optical transistor gets restructured for double duty" http://www.eetimes.com/showArticle.jhtml?articleID=179101523 A significant improvement in a hybrid optical transistor is being reported. This hybrid device operates as a gallium arsenide bipolar transistor that also emits light. That creates a fast-response optical output signal in tandem with the usual electronic output from a transistor. Now, refinements in the design make it possible to operate the transistor as a dual-input mixer, which would make it a highly compact optoelectronic component. Currently, such functionality has been demonstrated only in GaAS, but the recent successes in silicon optoelectronics may indicate that similar devices can be built in silicon. Reverse Engineering: "...backward and forward both run to need may they ,faster run to are computers If" http://www.americanscientist.org/template/AssetDetail/assetid/49610/page/1 Most of the machines we encounter in everyday life are one-way devices. Kitchen appliances turn bread into toast and cabbage into cole slaw, but they cannot perform the opposite transformations. Computers, too, are mostly irreversible machines ... That attitude is changing now. The reason is that reversible computing holds out the promise of dramatically lower power consumption, which is becoming an urgent need. Also, any computer based on quantum technology will necessarily be a reversible machine. "Boffins unveil nanotech chip design breakthrough" http://www.vnunet.com/vnunet/news/2150222/boffins-unveil-nanotech-chip US scientists have demonstrated a breakthrough method of computer chip lithography delivering imaging capabilities beyond those previously thought possible. The method, known as evanescent wave lithography, or EWL, is capable of optically imaging the smallest-ever semiconductor device geometry. "Nanotech expected to boom with $1 trillion market by 2015" http://news.webindia123.com/news/showdetails.asp?id=248001&cat=Business Nanotechnology, with far ranging applications in energy, medicine, agriculture and manufacturing, is expected to emerge into a 1 trillion dollar market by 2015, according to a journal. "FPGA family takes on more system functions" http://www.electronicstalk.com/news/lat/lat180.html The LatticeSC System Chip FPGA family is designed to provide the performance and connectivity essential for high-speed applications. Fabricated on Fujitsu's 90nm CMOS process technology using 300mm wafers, LatticeSC FPGAs are packed with features that accelerate chip-to-chip, chip-to-memory, high-speed serial, backplane and network data path connectivity to provide 'extreme performance'. "IBM chip architect guns for gigahertz" http://news.zdnet.com/2100-9584_22-6039293.html The gigahertz race is back on, and IBM's Brad McCredie is lacing up his shoes. Chipmakers have found it harder to kick up a processor's clock speed while actually getting more useful work out of a chip and avoiding inordinate electricity consumption. As a result, Intel, Sun Microsystems and Advanced Micro Devices have begun emphasizing other features--for example, squeezing multiple processing engines, called cores, onto a single slice of silicon or executing many instruction sequences, called threads, simultaneously. "Cadence Litho-Aware DFM Tool Aims to Improve Yield" http://www.reed-electronics.com/electronicnews/article/CA6307169.html Aiming to extend 193nm lithography to 45nm processes and beyond, San Jose-based EDA market leader Cadence Design Systems Inc. made strides in improving manufacturing yield with its Virtuoso Resolution Enhancement Technology (RET) suite of tools, meant to integrate lithography awareness directly into its Cadence Virtuoso custom design platform. "Intel Aims Core Duo at Embedded Developers" http://www.reed-electronics.com/electronicnews/article/CA6307530.html?ref=nbth Aiming to provide extended lifecycle support for developers of embedded solutions including industrial control, test and instrumentation, aerospace, defense and medical imaging systems, Santa Clara, Calif.-based Intel Corp. rolled out its Core Duo processor today. "A call for modern compilers" http://www.embedded.com/showArticle.jhtml?articleID=179101955 The compiler vendors are providing us with the same old crap we've put up with for 20 years. Snazzy integrated development environments (IDEs) are at least two decades old, though now the GUI versions are a lot prettier than old text-based DOS windows. Source-level debugging appeared about the same time. But compilers haven't improved in any significant way since then. What's going on? "Hidden in Plain Sight" http://www.acmqueue.com/modules.php?name=Content&pa=showpage&pid=361 Some of your largest performance problems could be hiding in broad daylight. Improvements in the observability of software can help you diagnose your most crippling performance problems. Learn what Sun's top development and support engineers have discovered. "Outsourcing: Navigating a maze of decisions" http://www.eetasia.com/ART_8800407023_480200_45c538f0_no.HTM The cheapest, fastest and best way to finish your chip design may be to get somebody else to do it. A complex web of providers, both domestic and offshore, will be happy to help. But successfully outsourcing IC design takes careful planning, strong project management and a realistic set of expectations. Is it worth it? "Securing pervasively connected embedded MCUs" http://www.embedded.com/shared/printableArticle.jhtml?articleID=165701128 Cascades of change are still occurring in relation to security in the MCU environment. Learn more about the state of the art and the direction things are headed. "Balancing cost vs. security for embedded design" http://www.eetasia.com/ART_8800407033_590626_c77add50_no.HTM In mainstream computing, it has been accepted that ubiquitous connectivity comes at the cost of constant vigilance and continued investment in security. However, users and developers of the embedded MCUs that populate industrial, building and home environments are only buying into the idea that security is a necessary long-term cost of doing business, with benefits that offset the expense of development, installation and long-term maintenance. "University of Wisconsin-Madison Researchers Explain Unexpected Conductivity of Nanoscale Silicon" http://www.azonano.com/news.asp?newsID=1830 When graduate student Pengpeng Zhang successfully imaged a piece of silicon just 10 nanometers-or a millionth of a centimeter-in thickness, she and her University of Wisconsin-Madison co-researchers were puzzled. According to established thinking, the feat should be impossible because her microscopy method required samples that conduct electricity. Learn how the impossible turned out to be possible. "IWLS 2006 Announced" http://www.iwls.org/ The International Workshop on Logic and Synthesis provides an international forum to promote research and exchange ideas about all aspects of integrated circuit and system synthesis, optimization, and verification. The workshop encourages early dissemination of ideas and results. Topics of interest include architectures and compilation, synthesis and optimization, power and timing analysis, design validation and verification, and design experiences, all applied at system description levels ranging from transistor-level to hardware-software interfaces. Implementation might be in synchronous or asynchronous CMOS, or any emerging technology. Submissions on modeling, analysis and tools targeting emerging technologies and platforms are particularly encouraged. ======================================================================== What is an And-Inverter Graph? -------------------------------- Alan Mishchenko Department of Electrical Engineering and Computer Sciences University of California, Berkeley An And-Inverter Graph (AIG) is a Boolean logic circuit composed only of inverters and two-input AND gates. AND gates correspond to graph nodes, and optional inverters are modeled as labels on the edges. AIGs can represent arbitrary Boolean functions and allow for efficient manipulations with such functions. Conversion from circuits to AIGs is fast and scalable. It only requires that every gate be expressed in terms of AND and NOT gates. This conversion does not lead to unpredictable increase in memory and runtime, making AIGs more attractive as functional representation compared to Sums-Of-Products (SOP) and Binary Decision Diagrams (BDDs). These older representations can also be viewed as circuits, but they impose somewhat artificial constraints, which often deprive them of scalability. For example, SOPs are circuits with at most two levels while ROBDDs are canonical, that is, require that input variables were evaluated in the same order on all paths. Circuits composed of simple gates, including AIGs, are an "ancient" research topic. The interest in AIGs started in the late 50's [1] and continued in the 70's when various local transformations have been developed. These transformations were implemented in several logic synthesis and verification systems, such as [2][3], which reduce circuits to improve area and delay during synthesis, or to speed up equivalence checking. Several important techniques were discovered early at IBM, such as combining and reusing multi-input logic expressions and subexpressions, now known as structural hashing. Recently there has been a renewed interest in AIGs as a functional representation for a variety of tasks in synthesis and verification. That is because representations popular in the 1990's (such as BDDs) have reached their limits of scalability in many of their applications. Another important development was the emergence in the last 5 years of much more efficient Boolean satisfiability (SAT) solvers. When coupled with AIGs as the circuit representation, they lead to remarkable speedups in solving a wide variety of Boolean problems. AIGs found successful use in diverse EDA applications. A well-tuned combination of AIGs and Boolean satisfiability made an impact on formal verification, including both model checking and equivalence checking [4]. Another recent work shows that efficient circuit compression techniques can be developed using AIGs [5]. There is a growing understanding that logic and physical synthesis problems can be solved using AIGs simulation and Boolean satisfiability compute functional properties (such as symmetries [6]) and node flexibilities (such as don't-cares, resubstitutions, SPFDs [7]). This work shows that AIGs are a promising /unifying/ representation, which can bridge logic synthesis, technology mapping, physical synthesis, and verification. This is, to a large extent, due to the simple and uniform structure of AIGs, which allow rewriting, simulation, mapping, placement, and verification to share the same data structure. In addition to combinational logic, AIGs have also been applied to sequential logic and sequential transformations. Specifically, the method of structural hashing was extended to work for AIGs with memory elements (such as D-flip-flops with an initial state, which, in general, can be unknown) resulting in a data structure that is specifically tailored for applications related to retiming [8]. Ongoing research includes implementing a modern logic synthesis system completely based on AIGs. The prototype called ABC [9] features an AIG package, several AIG-based synthesis and equivalence-checking techniques, as well as an experimental implementation of sequential synthesis. One such technique combines technology mapping and retiming in a single optimization step. It should be noted that these optimizations can be implemented using networks composed of arbitrary gates, but the use of AIGs makes them more scalable and easier to implement. ----------------------------------------- References: [1] L. Hellerman, "A catalog of three-variable Or-Inverter and And-Inverter logical circuits", IEEE Trans. Electron. Comput. vol. EC-12, June 1963, pp. 198-223. [2] A. Darringer, W. H. Joyner, Jr., C. L. Berman, L. Trevillyan, "Logic synthesis through local transformations," IBM J. Of Research and Development, Vol. 25(4), 1981, pp 272-280. [3] G. L. Smith, R. J. Bahnsen, H. Halliwell, "Boolean comparison of hardware and flowcharts". IBM J. Of Research and Development, Vol. 26(1), 1982, pp. 106-116. [4] A. Kuehlmann, V. Paruthi, F. Krohm, and M. K. Ganai, "Robust boolean reasoning for equivalence checking and functional property verification", IEEE Trans. CAD, Vol. 21(12), 2002, pp. 1377-1394. [5] P. Bjesse and A. Boralv, "DAG-aware circuit compression for formal verification", Proc. ICCAD '04, pp. 42-49. [6] K.-H. Chang, I. L. Markov, V. Bertacco, "Post-placement rewiring and rebuffering by exhaustive search for functional symmetries", Proc. ICCAD '05, pp. 56-63. [7] A. Mishchenko, J. S. Zhang, S. Sinha, J. R. Burch, R. Brayton, and M. Chrzanowska-Jeske, "Using simulation and satisfiability to compute flexibilities in Boolean networks", To appear in IEEE TCAD. [8] J. Baumgartner and A. Kuehlmann, "Min-area retiming on flexible circuit structures", Proc. ICCAD'01, pp. 176-182. [9] http://www.eecs.berkeley.edu/~alanmi/abc/ ======================================================================== Submission deadlines: --------------------- EUC'06 - Int'l Conference on Embedded And Ubiquitous Computing Seoul, Korea Aug 1 - 4, 2006 Workshop Proposal: Jan 22, 2006 Deadline: Feb 22, 2006 http://euc.wonkwang.ac.kr/ MWSCAS'06 - Midwest Symposium on Circuits and Systems San Juan, Puerto Rico Aug 6-9, 2006 Deadline: Feb 24, 2006 http://mwscas06.uprm.edu/ ISLPED'06 - Int'l Symposium on Low Power Electronics and Design Tegernsee, Germany Oct 4, 2006 Deadline: Feb 24, 2006 http://www.islped.org/ DAC'06 - SIGDA Ph.D. Forum at DAC San Francisco, CA Jul 25, 2006 Deadline: Feb 28, 2006 http://www.sigda.org/daforum/ EC'06 - Int'l Workshop on Embedded Computing Columbus, OH Aug 14, 2006 Deadline: Mar 06, 2006 http://juliet.stfx.ca/~lyang/icpp06-ec/ FPL'06 - Int'l Conference on Field Programmable Logic and Applications Madrid, Spain Aug 28-30, 2006 Deadline: Mar 10, 2006 http://fpl.org/ ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 Deadline : March 20, 2006 http://asap2006.grm.polymtl.ca/ PACT'06 - Int'l Conference on Parallel Architectures and Compilation Techniques Seattle, WA Sep 16-20, 2006 Deadline: Mar 27, 2006 http://www.pactconf.org VLSI-SoC'06 - Int'l Conference on Very Large Scale Integration French Riviera, France October 16 - 18, 2006 Deadline: Mar 27, 2006 http://tima.imag.fr/conferences/VLSI-SoC06/ SBCCI'06 - Symposium on Integrated Circuits and Systems Design Ouro Preto, Minas Gerais, Brazil Aug 28 - Sep 1, 2006 Deadline: Apr 2, 2006 http://www.sbc.org.br/sbcci FDL'06 - Forum on specification & Design Languages TU Darmstadt, Germany September 19 - 22, 2006 Deadline: Apr 3, 2006 http://www.ecsi-association.org/ecsi/fdl/fdl05/default.htm ICCAD'06 - Int'l Conference on Computer Aided Design San Jose, CA November 5 - 9, 2006 Deadline: Apr 19, 2006 http://www.iccad.com/ CODES-ISSS'06 - Int'l Conference on Hardware/Software Codesign and System Synthesis Seoul, Korea October 22 - 25, 2006 Deadline: May 8, 2006 http://www.codes-isss.org/ ======================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- FPGA'06 - Int'l Symposium on Field-Programmable Gate Arrays Monterey, CA Feb 22-24, 2006 http://conferences.ece.ubc.ca/isfpga2006/ SLIP'06 - System Level Interconnect Prediction Munich, Germany Mar 4-5, 2006 http://www.sliponline.org ISQED'06 - Int'l Symposium on Quality Electronic Design San Jose, CA Mar 27-29, 2006 http://www.isqed.org/ DATE'06 - Design Automation and Test in Europe Munich, Germany Mar 6-10, 2006 http://www.date-conference.com/ VLSI-TSA'06 - Int'l Symposium on VLSI Tech., Sys. & Applications VLSI-DAT'06 - Int'l Symposium on VLSI Design, Automation & Test Hsinchu, Taiwan Apr 24-26, 2006 http://vlsidat.itri.org.tw/2006/General/ IPDPS'06 - Int'l Parallel and Distributed Processing Symposium Rhodes Island, Greece Apr 25-29, 2006 http://www.ipdps.org/ GLSVLSI'06 - Great Lakes Symposium on VLSI Philadelphia, PA Apr 30 - May 2, 2006 http://www.glsvlsi.org/ ISCAS'06 - Int'l Symposium on Circuits and Systems Island of Kos, Greece May 21 - 24, 2006 http://www.iscas06.org/ ICSE'06 - Int'l Conference on Software Engineering Shanghai, China May 20 - 28, 2006 http://www.icse-conferences.org/2006/ DAC'06 - SIGDA Ph.D. Forum at DAC San Francisco, CA Jul 25, 2006 http://www.sigda.org/daforum/ DAC'06 - Design Automation Conference San Francisco, CA Jul 24 - 28, 2006 http://www.dac.com/ ASAP'06 - Int'l Conference on Application-specific Systems, Architectures and Processors Steamboat Springs, CO Sep 11-13, 2006 http://asap2006.grm.polymtl.ca/ ======================================================================== Upcoming funding opportunities ------------------------------- DOD Electronics Design for Cold Environments (CRREL-66) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf Sensors, Sensor Systems, Data Acquisition, Processing, and Transmission Systems (ITL-6) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf High Performance Computing (HPC) and Networking (ITL-4) Deadline: Continuous http://www.mvk.usace.army.mil/contract/docs/FY2006BAA1.pdf NSF Integrative Graduate Education and Research Traineeship Program . NSF 06-525 Deadline: March 27, 2006 http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=12759&org=CISE&from=home Cyber Trust . NSF 05-518 Deadline: March 6, 2006 http://www.nsf.gov/pubs/2006/nsf06517/nsf06517.htm Mathematical Sciences: Innovations at the Interface with the Sciences and Engineering - NSF 05-622 Deadline: March 01, 2006 http://www.nsf.gov/pubs/2005/nsf05622/nsf05622.htm Information and Intelligent Systems: Advancing Collaborative and Intelligent Systems and their Societal Implications - NSF 05-551 Deadline: April 18, 2006; April 20, 2006 http://www.nsf.gov/publications/pub_summ.jsp?ods_key=nsf05551 DARPA Spoken Language Communication and Translation System for Tactical Use (TRANSTAC) Deadline: March 24, 2006 (Initial Closing) http://www.darpa.mil/ipto/solicitations/open/06-21_PIP.htm Advanced Soldier Sensor Information System and Technology Deadline: August 04, 2006 http://fedbizopps.cos.com/cgi-bin/eps/spg/ODA/DARPA/CMO/BAA04-38/listing.html?notice=MOD NAVSEA Science and Technology BAA - Countermeasures Technology Deadline: Open until March 21, 2006 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Science and Technology BAA . Audition and Communication Deadline: Open until March 21, 2006 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Science and Technology BAA . Test and Evaluation Deadline: Open until March 21, 2006 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Fellowship NASA Summer Faculty Research Opportunities (NSFRO) Deadline: March 14, 2006; May 02, 2006 http://www.asee.org/resources/fellowships/nsfro/general.cfm Sloan Research Fellowships Deadline: September 15, 2006 http://www.sloan.org/programs/scitech_fellowships.shtml ======================================================================== Call for Nominations: Advanced Member Grades In the ACM ----------------------------------------------------------- ACM has three distinct member grades to recognize the professional accomplishments of our members: Senior Member - is a new member grade recognizing those ACM members, with at least 10 years of professional experience, that have demonstrated performance and accomplishment that set them apart. Distinguished Engineer, Scientist, or Member - is a new member grade recognizing those ACM members, with at least 15 years of professional experience that have made significant accomplishments or achieved a significant impact on the computing field. Fellow - is ACM's most prestigious member grade recognizing the top 1% of ACM members for their outstanding accomplishments in computing and information technology and/or outstanding service to ACM and the larger computing community. Criteria Senior Member . Five years continuous (Professional) membership in ACM . Ten years of professional experience . Demonstrated performance that sets the member apart from peers . Three endorsements from colleagues (not necessarily ACM members) in the field Distinguished Engineer, Scientist, or Member . Five years continuous (Professional) membership in ACM . Fifteen years of professional experience . Significant accomplishment in, or a significant impact on, the computing field . Four endorsements from colleagues in the field. Three of these endorsements must be from ACM Members. It is recommended, but not required, that at least two of these endorsements be from ACM Fellows. Ideally, one of the four endorsements will be from a current or past employer or client. Fellow . Five years continuous (Professional) membership in ACM . No specific requirement for years of professional experience . Outstanding accomplishments in computing and information technology and/or outstanding service to ACM and the larger computing community . Five to eight endorsements from current ACM Professional Members - ideally ACM Fellows. Nomination Procedures All nominations for advanced ACM member grades must be made through the ACM website: Senior Members are self-nominating Distinguished Engineers, Scientists, Members can be self-nominating or may be nominated by a current ACM Professional Member Fellows must be nominated by an ACM Professional Member Notes: . In meeting the requirements for professional experience, educational experience is credited as follows: - 3 years if the candidate holds a baccalaureate degree - 4 years if the candidate holds a masters degree - 5 years if the candidate holds a doctorate . For all grades, candidates must have been an ACM Professional Members for at least five years immediately preceding the final date for submission of the respective nomination. . Although there is a natural progression implied within these three grade levels, this progression is not compulsory, i.e., if a candidate meets the requirements of the membership grade it is not necessary to advance from one grade level to the next. . Endorsers for Senior Member and Distinguished Engineer, Scientist, or Member must attest that: - They know the candidate and their work - The candidate has accurately described their achievements - The accomplishments outlined in the nomination meet the endorsers. best understanding of the criteria for Senior and Distinguished Member. Deadlines Senior Member nominations and endorsements must be received by May 31, 2006. Distinguished Engineer, Scientist, Member nominations and endorsements must be received by July 31, 2006. Fellow nominations and endorsements must be received by September 8, 2006. Recognition ACM Senior Members and Distinguished Members will receive a certificate and a specially annotated ACM membership card. There will be an announcement on the ACM Web site and in Communications of the ACM listing the names of the Senior Members and Distinguished Members. ACM Fellows will receive a certificate, a specially annotated ACM membership card and an ACM Fellow lapel pin. Their names will be listed in an issue of Communications of the ACM and a letter of recognition will be sent to the chief executive at the Fellow's place of employment. Formal induction ceremonies and presentation of Fellow certificates and pins will take place at the next annual ACM Awards Banquet. Questions Please send any questions you may have about the Senior Member, Distinguished Member or Fellows Programs to: Senior@acm.org Distinguished@acm.org Fellow@acm.org ======================================================================== Call For Papers ---------------- 2nd IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH'2006) http://www.nanoarch.org June 17, 2006 Boston Park Plaza Hotel, Boston, MA, USA * Several NSF supported travel grants will be available for students participating in NANOARCH 2006. Current defect tolerance, fault-tolerance and manufacturing test techniques are designed under the assumption that a system under test is composed largely of correctly functioning units. However, this assumption is severely tested in emerging nanoelectronics such as molecular electronics, quantum electronics, single electron transistors and carbon nanotubes and nanowires. In these nanoelectronics, self-assembly based fabrication results in failures rates an order of magnitude higher than in traditional CMOS. Consequently, defect and fault tolerance - at the physical, circuit and most importantly at the system level- is an enabling technology for building reliable nanoelectronic systems. NANOARCH will investigate novel defect and fault tolerance architectures targeting these highly unreliable nanoelectronics. The workshop will be a forum for presenting theoretical, simulation and case studies on new defect models, defect and fault tolerance architectures, associated experimental reliability evaluation and validation frameworks and computer aided simulation and design tools for these emerging nanoelectronics. Topics of interest include but are not limited to: .Defect tolerant nanoelectronic architectures at device, circuit, and system level .Fault tolerant nanoelectronic architectures at the device, circuit, and system level .Emerging computational paradigms for nanoelectronics .Modeling and simulation of novel nanoelectronic architectures and concepts .Implementing micro-architectural concepts using nanoarchitectural building blocks .Dynamic reconfiguration in nanoelectronic architectures .Defect and fault models in emerging nanoelectronic device technologies .Manufacture testing methodologies for nanoelectronic architectures .Yield models, yield analysis and yield enhancement in nanoelectronics .CAD targeting defect and fault-tolerant nanoelectronic architectures The Program Committee invites authors to submit papers up to 8 pages in length, describing original, unpublished recent work. Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. Electronic submission through the workshop website is required. The submission of a paper proposal will be considered evidence that upon acceptance, the author(s) will present their paper at the workshop. Final versions of accepted papers will be included in the NANOARCH Workshop Digest Important deadlines: (please submit to the workshop website http://www.nanoarch.org) Abstracts: March 20, 2006 Paper: March 27, 2006 Acceptance notification: May 1, 2006 Final version of papers: June 1, 2006 GENERAL CHAIR R. Karri, Polytechnic U PROGRAM CHAIR A. Orailoglu, UC San Diego SPECIAL ISSUE CO-CHAIRS M. Stan, U Virginia, and K. Likharev, Stony Brook SPECIAL SESSIONS CHAIR D. Hammerstrom, Portland State PUBLICITY CO-CHAIRS S. Levitan, U. Pittsburgh, and J. Chen, National Institute of Nanotechnology & U Alberta INDUSTRY LIAISON W. Joyner, SRC NANO TC LIAISON R. Kapur, Synopsys ASIAN LIAISON K. Kim, Incheon PUBLICATIONS CHAIR D. Sorin, Duke E-MEDIA CHAIR I. Bayraktaroglu, Sun PROGRAM COMMITTEE Iris Bahar, Brown U Valeriu Beiu, Washington State U Shamik. Das, MITRE Andre DeHon, Caltech Chris Dwyer, Duke U James Ellenbogen, MITRE Haldun Hadimioglu, Polytechnic U Niraj Jha, Princeton Alexander Khitun, UC Los Angeles Yusuf Leblebici, EPFL Meyya Meyyappan, NASA Ames Kaushik Roy, Purdue U Alberto Sangiovanni-Vincentelli, UC Berkeley Sandeep Shukla, Virginia Tech Kang Wang, UC Los Angeles Kaijie Wu, UIC ======================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. First time users will be required to choose a password.) ======================================================================== Notice to Authors The contents of the ACM SIGDA newsletters are typically made available through the ACM Digital Library, the SIGDA Web site and other Web sites, such as the Wikipedia. If you wish your contribution to not be posted on any of those sites, please contact the editors of the newsletter. ========================================================================