======================================================================== SIGDA -- The Resource for EDA Professionals www.sigda.org ======================================================================== 15 December 2005 ACM/SIGDA E-NEWSLETTER Vol. 35, No. 24 Online archive: http://www.sigda.org/newsletter ======================================================================== Contents of this E-NEWSLETTER: (1) Current DA TechNews issue Thursday December 15 2005 From: "Qing Wu" (2) "What is formal verification?" Thursday December 15 2005 Contributing author: Dr. Per Bjesse From: "Igor Markov" (3) Paper Submission Deadlines Thursday December 15 2005 From: "Hai Zhou" (4) Upcoming Conferences and Symposia Thursday December 15 2005 From: "Hai Zhou" (5) Upcoming Funding Opportunities Thursday December 15 2005 From: "Qinru Qiu" (6) Call For White Papers: SRC Thursday December 15 2005 From: "William H. Joyner, Jr." "W. Dale Edwards" (7) Call For Proposals: DAC Graduate Scholarships Thursday December 15 2005 From: "Diana Marculescu" (8) Call For Papers: GLS-VLSI Thursday December 15 2005 From: "Hai Zhou" ======================================================================== Dear ACM/SIGDA members, You can find the content of the current issue of SIGDA TechNews at http://www.acm.org/da_technews/current/homepage.html As always, we welcome your comments and suggestions. If you would like to participate or contribute to the content of the E-Newsletter, please feel free to contact any of us. Happy Holidays! Igor Markov and Qing Wu, E-Newsletter Editors; Qinru Qiu, E-Newsletter Associate Editor; Hai Zhou, E-Newsletter Associate Editor; ======================================================================== DA TechNews headlines ----------------------- "SystemVerilog Won't Kill 'e,' Say Proponents" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item1 "IC Makers Face Tricky 65nm Transition" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item2 "Hyperthreading Hurts Server Performance, Say Developers" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item3 "IBM Sees Bright Light With Carbon Nanotubes" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item4 "Reducing Power Consumption" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item5 "The Key to Estimating Final Chip Cost" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item6 "Cellphone Squeeze Play: Key Parts on One Chip" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item7 "OASIS in the Valley" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item8 "VLSI Design Conference to Be Held in Hyderabad" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item9 "Plastic Diode Could Lead to Flexible, Low Power Computer Circuits, Memory" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item10 "Sun Microsystems Will Offer New Generation of Processors" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item11 "High-k Dielectric Not Necessary for 45nm Process" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item12 "Light Pedaling" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item13 "The End of Moore's Law" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item14 "Mobile Robots Get Serious" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item15 "Semiconductor Workforce Demands and Opportunities" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item16 "The 5 Most Enduring Principles" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item17 "Verifying Complexity: Assertion-Based Verification of Platform FPGA Designs" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item18 "ASICs Carve a Cost-Savvy Niche" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item19 "FPGA Co-processor Design Flow for Video, Imaging Applications" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item20 "Digital RF and Handset Integration" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item21 "Mixed-Orientation Transistors Built Without SOI" http://www.acm.org/da_technews/articles/2005-3/1124t.html#item22 ======================================================================== What is formal verification? -------------------------------------------- Per Bjesse Synopsys Inc. Formal verification is the use of mathematical techniques to ensure that a design conforms to some precisely expressed notion of functional correctness. Concretely, assume that you have (1) a model of a design, (2) some description of the environment that the design is supposed to operate in, and (3) some properties that the design is intended to fulfill. Given this information, you may want to search for some input patterns that the environment could generate that will violate the properties. Classical approaches to demonstrating that such input stimuli exist are random simulation, or directed test. Formal verification is an alternative approach that can be used both to search for inputs sequences that violate the properties, and prove that the properties always hold in the case when no such stimuli exist. Formal verification can be applied to designs described at many different levels of abstraction, ranging from the gate level, to RTL implementations, and in some cases even to transaction level models described in standardized programming languages. There are several different use models for formal verification. Some design teams use it to boost the coverage of random simulation and hunt for bugs, whereas others make full blown use of it to conclusively prove that certain properties hold. State-of-the-art tools integrate formal verification engines with simulation in a seamless way. A particular formal verification problem of great interest in EDA is equivalence checking. Here, the property that is checked is whether two different designs always have the same input/output behavior with respect to some notion of equivalence. Special algorithms are used when it is known that the two designs differ only in restricted ways, for example when combinational optimization only has been used to derive one from the other. Compute resources required by formal verification algorithms generally grow very quickly as design sizes increase. Current formal verification research aims to increase the capacity of the design analysis algorithms, and to make formal verification usable earlier in the design cycle. For equivalence checking, hot topics include better capacity for data path verification and support for verification of sequential transformations. For an overview of the field, see the following survey articles: A. Gupta, "Formal Hardware Verification Methods: A Survey", Formal Methods in System Design, Vol. 1, pp. 151-238, 1992. C. Kern and M. Greenstreet, "Formal Verification in Hardware Design: A Survey", ACM Transactions on Design Automation of E. Systems, Vol. 4, April 1999, pp. 123-193. T. Kropf: Introduction to Formal Hardware Verification, Springer Verlag, 1999. C-J. Seger, "An Introduction to Formal Verification", Technical Report 92-13, University of British Columbia, Department of Computer Science, Vancouver, B.C., Canada, June 1992. ======================================================================== Submission deadlines: --------------------- Tau'06 - Int'l Workshop on Timing Issues in the Specification and Synthesis of Digital Systems San Jose, CA Feb 27 - 28, 2006 Deadline: Dec 19, 2005 http://www.tauworkshop.com/ DRS'06 - Workshop on Dynamically Reconfigurable Systems Frankfurt, Germany Mar 16, 2006 Deadline: Dec 16, 2005 http://www.mr.inf.tu-dresden.de/arcs2006/ FCCM'06 - Symposium on Field-Programmable Custom Computing Machines Napa Valley, CA Apr 24 - 26, 2006 Deadline: Jan 13, 2006 http://www.fccm.org/ GLSVLSI'06 - Great Lakes Symposium on VLSI Philadelphia, PA Apr 30 - May 2, 2006 Deadline: Jan 13, 2006 http://www.glsvlsi.org/ RSP'06 - Int'l Workshop on Rapid System Prototyping Chania, Crete Jun 14-16, 2006 Deadline: Jan 14, 2006 http://www.rsp-workshop.org/ EUC'06 - Int'l Conference on Embedded And Ubiquitous Computing Seoul, Korea Aug 1 - 4, 2006 Workshop Proposal: Jan 22, 2006 Deadline: Feb 22, 2006 http://euc.wonkwang.ac.kr/ MWSCAS'06 - Midwest Symposium on Circuits and Systems San Juan, Puerto Rico Aug 6-9, 2006 Deadline: Feb 24, 2006 http://mwscas06.uprm.edu/ FLoC'06 - Federated Logic Conference Seattle, WA Aug 12-21, 2006 The following six conferences will participate in FLoC: - Conference on Computer-Aided Verification (CAV). - International Conference on Logic Programming (ICLP). - International Joint Conference on Automated Deduction (IJCAR). - IEEE Symposium on Logic in Computer Science (LICS). - Conference on Rewriting Techniques and Applications (RTA). - International Conference on Theory and Applications of Satisfiability Testing (SAT). http://research.microsoft.com/floc06/ ISLPED'06 - Int'l Symposium on Low Power Electronics and Design Tegernsee, Germany Oct 4, 2006 Deadline: Feb 24, 2006 http://www.islped.org/ FPL'06 - Int'l Conference on Field Programmable Logic and Applications Madrid, Spain Aug 28-30, 2006 Deadline: Mar 10, 2006 http://fpl.org/ PACT'06 - Int'l Conference on Parallel Architectures and Compilation Techniques Seattle, WA Sep 16-20, 2006 Deadline: Mar 27, 2006 http://www.pactconf.org SBCCI'06 - Symposium on Integrated Circuits and Systems Design Ouro Preto, Minas Gerais, Brazil Aug 28 - Sep 1, 2006 Deadline: Apr 2, 2006 http://www.sbc.org.br/sbcci ======================================================================== Upcoming symposia, conferences and workshops: --------------------------------------------- ATS'05 - Asian Test Symposium Kolkata, India Dec 18-21, 2005 http://www.iitkgp.ac.in/ats05/ VLSI/ES'06 - Intl. Conference on VLSI Design and Intl. Conference on Embedded Systems: Mobile Embedded Systems Hyderabad, India Jan 3-7, 2006 http://vlsi.nj.nec.com/ SODA'06 - Symposium on Discrete Algorithms Miami, Florida Jan 22-24, 2006 http://www.siam.org/meetings/DA06/ ASP-DAC'06: Asia and South Pacific Design Automation Conference Yokohama City, Japan Jan 24-27, 2006 http://www.aspdac.com/aspdac2006/ FPGA'06 - Int'l Symposium on Field-Programmable Gate Arrays Monterey, CA Feb 22-24, 2006 http://conferences.ece.ubc.ca/isfpga2006/ SLIP'06 - System Level Interconnect Prediction Munich, Germany Mar 4-5, 2006 http://www.sliponline.org ISQED'06 - Int'l Symposium on Quality Electronic Design San Jose, CA Mar 27-29, 2006 http://www.isqed.org/ DATE'06 - Design Automation and Test in Europe Munich, Germany Mar 6-10, 2006 http://www.date-conference.com/ VLSI-TSA'06 - Int'l Symposium on VLSI Tech., Sys. & Applications VLSI-DAT'06 - Int'l Symposium on VLSI Design, Automation & Test Hsinchu, Taiwan Apr 24-26, 2006 http://vlsidat.itri.org.tw/2006/General/ IPDPS'06 - Int'l Parallel and Distributed Processing Symposium Rhodes Island, Greece Apr 25-29, 2006 http://www.ipdps.org/ GLSVLSI'06 - Great Lakes Symposium on VLSI Philadelphia, PA Apr 30 - May 2, 2006 http://www.glsvlsi.org/ ======================================================================== Upcoming funding opportunities ------------------------------- DOI: Innovative Research to support and Advance Quantum Information Science Objectives Deadline: January 9, 2006 http://www.fbo.gov/spg/DOI/OS/SAB/BAA06QIS/SynopsisP.html NRL: Spacecraft Technology Deadline: December 31, 2006 http://heron.nrl.navy.mil/contracts/baa.htm NSF: Cyber Trust . NSF 05-518 Deadline: March 6, 2006 http://www.nsf.gov/pubs/2006/nsf06517/nsf06517.htm Mathematical Sciences: Innovations at the Interface with the Sciences and Engineering - NSF 05-622 Deadline: March 01, 2006 http://www.nsf.gov/pubs/2005/nsf05622/nsf05622.htm Computer Systems Research (CSR) - NSF 05-629 Deadline: January 11, 2006 http://www.nsf.gov/pubs/2005/nsf05629/nsf05629.htm Science of Design: Software-Intensive Systems: NSF 05-620 Deadline: January 06, 2006 http://www.nsf.gov/pubs/2005/nsf05620/nsf05620.htm Scientific Computing Research Environments for the Mathematical Sciences Deadline: January 26, 2006 http://www.nsf.gov/pubs/2005/nsf05627/nsf05627.htm Information and Intelligent Systems: Advancing Collaborative and Intelligent Systems and their Societal Implications - NSF 05-551 Deadline: April 18, 2006; April 20, 2006 http://www.nsf.gov/publications/pub_summ.jsp?ods_key=nsf05551 DARPA Advanced Soldier Sensor Information System and Technology Deadline: August 04, 2006 http://fedbizopps.cos.com/cgi-bin/eps/spg/ODA/DARPA/CMO/BAA04-38/listing.html?notice=MOD AFRL AFRL BAA 2005-1 . Space Electronics Deadline: Ongoing until superceded http://www.afosr.af.mil/pdfs/BAA2005-1.pdf AFRL BAA 2005-1 . Atomic and Molecular Physics Deadline: Ongoing until superceded http://www.afosr.af.mil/pdfs/BAA2005-1.pdf AFRL BAA 2005-1 . Remote Sensing and Imaging Deadline: Ongoing until superceded http://www.afosr.af.mil/pdfs/BAA2005-1.pdf AFRL BAA 2005-1 . Optoelectronics: Components and Information Processing Deadline: Ongoing until superceded http://www.afosr.af.mil/pdfs/BAA2005-1.pdf AFRL BAA 2005-1 . Quantum Electronic Solids Deadline: Ongoing until superceded http://www.afosr.af.mil/pdfs/BAA2005-1.pdf AFRL BAA 2005-1 . Semiconductor Materials Deadline: Ongoing until superceded http://www.afosr.af.mil/pdfs/BAA2005-1.pdf AFRL BAA 2005-1 . Sensors in the Space Enviroment Deadline: Ongoing until superceded http://www.afosr.af.mil/pdfs/BAA2005-1.pdf AFRL BAA 2005-1 . High Density Optical Memory Deadline: Ongoing until superceded http://www.afosr.af.mil/pdfs/BAA2005-1.pdf NAVSEA Science and Technology BAA - Countermeasures Technology Deadline: Open until March 21, 2006 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Science and Technology BAA . Audition and Communication Deadline: Open until March 21, 2006 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ Science and Technology BAA . Test and Evaluation Deadline: Open until March 21, 2006 http://www.npt.nuwc.navy.mil/contract/info/baa2004/ USACE Engineer Research and Development Center BAA . High Performance Computing and Networking (ITL-4) Deadline: Ongoing until superceded http://www.mvk.usace.army.mil/contract/docs/2005BAA.pdf Engineer Research and Development Center BAA . Sensing (EL-1) Deadline: Ongoing until superceded http://www.mvk.usace.army.mil/contract/docs/2005BAA.pdf Engineer Research and Development Center BAA . Innovative Technologies for Rapid Characterization and Monitoring of Hazardous Waste Sites (EL-1) Deadline: Ongoing until superceded http://www.mvk.usace.army.mil/contract/docs/2005BAA.pdf Engineer Research and Development Center BAA . Artificial Intelligence (CRREL-59) Deadline: Ongoing until superceded http://www.mvk.usace.army.mil/contract/docs/2005BAA.pdf Engineer Research and Development Center BAA . Electronics Design for Cold Environments (CRREL-66) Deadline: Ongoing until superceded http://www.mvk.usace.army.mil/contract/docs/2005BAA.pdf Fellowship NASA Summer Faculty Research Opportunities (NSFRO) Deadline: March 14, 2006; May 02, 2006 http://www.asee.org/resources/fellowships/nsfro/general.cfm Sloan Research Fellowships Deadline: September 15, 2006 http://www.sloan.org/programs/scitech_fellowships.shtml ======================================================================== Call For White Papers ----------------------- SRC white papers in logic and physical design Due: January 6th, midnight EST Colleagues: The Computer-Aided Design and Test science area of SRC is soliciting white papers in logic and physical design. One page white papers are due January 6. A limited number of full proposals will be accepted based on the white paper submissions, and a subset of these proposals will be selected for anticipated three-year contracts beginning July 1, 2006. Interested researchers should note the proposal and review schedule, needs document, and instructions for web-based white paper submission on the SRC Web site at http://www.src.org/fr/S200510_Call.asp. White papers that address the following focus areas are likely to generate greater interest from SRC member companies: 1) Power analysis and reduction tools and techniques 2) System-level design tools, including tools for developing multicore designs 3) Tools and techniques addressing manufacturability; handling a full range of process, temperature and voltage; and mitigating the impact of random, systematic and environmental variations White papers offering incremental improvements in traditional extraction, physical design, modeling, and optimization will receive limited consideration. Bill & Dale William H. Joyner, Jr., william.joyner@src.org W. Dale Edwards, dale.edwards@src.org Semiconductor Research Corporation(r) Box 12053 Research Triangle Park, NC 27709 919-941-9450 fax 919-941-9400 main number www.src.org ======================================================================== Call For Proposals: DAC Graduate Scholarships ------------------------- $24,000 DAC scholarships to support graduate research and study --------------------------------------------------------------- The 43rd Design Automation Conference plans to award scholarships to support graduate research and study in electronic design automation and circuit design. These scholarships are intended to support graduate students of faculty investigators at universities trying to establish new programs in electronic design automation or circuit design and/or graduate students of young faculty investigators (assistant rank, non-tenured) working in electronic design automation or circuit design. These scholarships are awarded directly to a university for the faculty investigator to expend in accordance with his or her proposal. The university is free to use the scholarship funds in direct support of one or more of the graduate students named in the proposal, in the manner outlined in the proposal, except that the funds shall not be used to support indirect costs or overhead. PROPOSAL FORMAT All applications must be submitted via email to gradscholar@dac.com by February 24, 2006. Submissions open Dec. 5, 2005. You will receive an acknowledgement of receipt of any email sent to the above address. A PDF of the application for the scholarship, either new or renewal, should be submitted by the faculty investigator and must include: * A brief (3 pages maximum) curriculum vitae of the faculty investigator; * A brief (2 pages maximum) biography of each student proposed for the scholarship presenting their credentials and outlining their career goals and objectives; * A brief (5 pages maximum) proposal describing the research to be conducted and the way in which the scholarship funds are to be expended; * A brief (1 page maximum) statement of the impact of the scholarship on the design program at the faculty investigator's institution; * A listing of all current and pending support (indicating support provider, support duration, and support dollar amount) for the faculty investigator and each student involved in the proposal; and * An indication of any previous DAC Graduate Scholarship awarded to the faculty investigator. SELECTION CRITERIA Scholarships will be awarded based on the following criteria: * Quality and applicability of the proposed research; * Impact of the award on the program at the faculty investigator's institution; * Academic credentials of the student(s); * Need (preference will be given to students and programs that can demonstrate financial need). RESTRICTIONS AND RESPONSIBILITIES The scholarship funds must only be used to support the students and research named in the winning proposals. Because the award decisions are made based on the named students and specified research, no substitutions may be made without express written permission. Without such permission, the scholarship recipient will forfeit the award if the conditions of the research proposed change. Scholarships can be awarded in support of new projects or for one renewal of a previous DAC Graduate Scholarship. An application from either the same faculty investigator or student awardee from a previous year is considered a renewal application. The faculty investigator must submit a brief report of the year's activities supported by the scholarship for publication in the newsletters of the sponsoring organizations (ACM/SIGDA and/or IEEE CAS/CANDE). This report should be submitted at the conclusion of the year supported. For further information, contact the Chair of the 2006 Selection Committee, Prof. Diana Marculescu at: 412-268-1167 or by email at: dianam@ece.cmu.edu. ======================================================================== Call For Papers - GLS-VLSI ----------------------------- ACM GLSVLSI 2006 Call For Papers http://www.glsvlsi.org/ The 16th edition of ACM GLSVLSI will be held on April 30, 2006 - May 2, 2006 in Philadelphia, Pennsylvania. Original, unpublished papers, describing research in the general area of VLSI are solicited. Both theoretical and experimental research results are welcome. Proceedings will be published by the ACM and will be included on the SIGDA compendium CD-ROM. Program Tracks: - VLSI Design: design of ASICs, microprocessors and micro-architectures, embedded processors, analog/digital/mixed-signal systems, multi-chip modules, FPGAs. - VLSI Circuits: analog/digital/mixed-signal circuits, RF and communication circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits. -Computer-Aided Design (CAD): hardware/software co-design, logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction), algorithms and complexity analysis. - Low Power and Power Aware Design: circuits, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools. - Testing, Reliability, Fault-Tolerance: digital/analog/mixed-signal testing, design for testability and reliability, online testing techniques, static and dynamic defect- and fault-recoverability, and variation-aware design. - Emerging Technologies: nanotechnology, molecular electronics, quantum devices, biologically-inspired computing, single electron transistors, resonant tunneling devices, VLSI aspects of sensor and sensor network, and CAD tools for emerging technology devices and circuits. Paper submission deadline: January 13, 2006, 5:00 pm (PST) Acceptance notification: February 20, 2006 Camera ready paper due: March 6, 2006 Paper Submission: Authors are invited to submit full-length (6 pages maximum), original, unpublished papers along with an abstract of at most 200 words. To enable blind review, the author list should be omitted from the main document. Previously published papers or papers currently under review for other conferences/journals will not be considered. Electronic submission in Adobe PDF format to the www.glsvlsi.org website is required. Author and contact information (name, street/mailing address, telephone, fax, e-mail) must be entered during the submission process. Paper Format: To allow reduced turn-around time for accepted papers, GLSVLSI 2006 submissions should be in camera-ready two-column format, following the ACM proceedings specifications located at: http://www.acm.org/sigs/pubs/proceed/template.html and the classification system detailed at: http://www.acm.org/class/1998/. Symposium Presentations: Papers will be accepted for long, short, or poster presentation at the symposium. Every accepted paper must have at least one author register for and attend the symposium. Best Student Paper Award: A "Best Student Paper Award" will be voted on by the technical program committee. Only papers with a student as first author will be eligible. A laptop, generously donated by Intel, will be awarded to the winner at the symposium. ======================================================================== (This ACM/SIGDA E-NEWSLETTER is being sent to all persons on the ACM/SIGDA mailing list. To manage your subscription, go to "Subscriber's corner" on http://listserv.acm.org/ - you need to login using the email address where this newsletter is delivered. First time users will be required to choose a password.) ========================================================================