ISPD 2007 Global Routing Contest Announcements



ISPD 2007 Global Routing Contest

Continuing the tradition of spirited competition, the ISPD 2007 Steering Committee is pleased to announce a global routing contest, sponsored by SRC and IEEE-CEDA. Like the prior placement contests, a set of benchmarks will be released; teams are invited to produce global routing solutions, with the best results winning fame, recognition, and a grand prize. There will be an additional prize awarded by the IEEE Council of EDA (CEDA) for the best results on the multi-layer examples by a router openly available to all research groups. If the best results overall are obtained by an openly available router, it will win both the prizes.

The global routing solutions will be evaluated on the following metrics:

There will be two sets of benchmarks.

There will be separate prizes for each set of benchmarks (and it is entirely possible that one global router could win both groups).

REGISTRATION: If you are interested in participating in the contest, please send email to Dr. Gi-Joon Nam (gnam@us.ibm.com).  

CONTEST SCHEDULE:

FILE FORMAT for Three Dimensional Benchmarks

The file format for the global routing contest is illustrated, with comments in italics (these will not be in actual input files). This example illustrates a problem with five routing layers (note the number of # marks on the vertical and horizontal capacity lines).

grid # # # (x grids, y grids, number of layers)
vertical capacity # # # # # (vertical capacity by default on each layer)
horizontal capacity # # # # #
minimum width # # # # #
minimum spacing # # # # #
via spacing # # # # #
lower_left_x lower_left_y tile_width tile_height

num net #
netname id_# number_of_pins minimum_width
x y layer
x y layer
...
[repeat for the appropriate number of nets]

# capacity adjustments (to model contestion)
column row layer column row layer reduced_capacity_level
[repeat for the number of capacity adjustments]

There are a number of changes from the Labyrinth format:

Calculation of capacity is more complex than is done in typical academic global routing tools; our objective is to raise the bar slightly. Each global routing tile will have a capacity; this is a measure of the available space, not the number of global routing tracks. If the minimum wire width is 20, the minimum spacing 10, and the capacity of a tile is given as 450, this corresponds to 15 minimum width tracks (15 * (20 + 10)) . The capacity specified as the default value may be different than the width or height of a tile: in general, it is desirable to have routing utilization of a tile be below 70% of capacity, as higher values are difficult for detail routers to complete.

SAMPLE FILES

A simple 2-d routing problem, with illustrations.  Input.  Output.  Description.

A simple 3-d routing problem, with illustrations.  Input.  Output.  Description.

CONTESTANTS

Team Name Contact Email Address Other Authors
UCLA FlexRouter Lei He (U of California, Los Angeles) lhe@ee.ucla.edu Tom Tong Jing (tomjing@ucla.edu), Zhen Cao, Paul Mesa, Yiyu Shi, Yu Hu
Team 3 Pei-Ci Wu (National Tsing-Hua University, Taiwan) g944310@oz.nthu.edu.tw Kuang-Yao Lee, Jhih-Rong Gao, Tsung-Hsien Lee, Yen-Jung Chang, Ting-Chi Wang
Team 4 Guojie Luo (U of California, Los Angeles) gluo@cs.ucla.edu Yan Zhang (zhangyan@cs.ucla.edu), Jason Cong (cong@cs.ucla.edu)
Instant Karma Patrick Madden (SUNY, Binghamton) pmadden@acm.org  
Box Router David Pan (U of Texas, Austin) dpan@ece.utexas.edu Minsik Cho (thyeros@cerc.utexas.edu)
Team 8 Chris Chu (Iowa State University) cnchu@iastate.edu Yanheng Zhang (zyh@iastate.edu)
Team 9 Huang-Yu Chen (National Taiwan University, Taiwan) yellowfish@eda.ee.ntu.edu.tw Chin-Hsiung Hsu (arious@eda.ee.ntu.edu.tw), Chung-Wei Lin (enorm@eda.ee.ntu.edu.tw), Yao-Wen Chang (ywchang@cc.ee.ntu.edu.tw)
Team 10 Yih-Lang Li(National Chiao-Tung University, Taiwan) dkr.cs94g@nctu.edu.tw Jyun-Yi Lin (quasarsbubu@gmail.com), Ken-Ren Dai (bubu.cs94g@nctu.edu.tw), Yih-Lang Li (dkr.cs94g@nctu.edu.tw)
FGR Jarrod Roy (U of Michigan) royj@eecs.umich.edu Igor Markov (imarkov@eecs.umich.edu)
Team 13 Tai-Chen Chen (National Taiwan University, Taiwan) tcchen@eda.ee.ntu.edu.tw Kai-Chi Hsu (aaron@eda.ee.ntu.edu.tw), Shi-Lun Huang (kethy@eda.ee.ntu.edu.tw), Meng-Ziang Li (u1501027@cc.ntu.edu.tw), Yao-Wen Chang (ywchang@cc.ee.ntu.edu.tw)
Team 14 Hung-Ming Chen (National Chiao-Tung University, Taiwan) hmchen@mail.nctu.edu.tw  
MaizeRouter Michael D. Moffitt (U of Michigan) michael.d.moffitt@gmail.com  
Team 16 Soheil Modirzadeh (Cadence Design Systems) soheil@cadence.com Nora Chu (norac@cadence.com)
Bockenem(Stau auf der A7) Artur Quiring (Cadence Berkely Lab) artur@cadence.com Philip Chong (pchong@cadence.com), Christoph Albrecht (calb@cadence.com)

 

 

Openly Available Tools

What does "openly available for research" mean?  In this case, the intent is to foster an academic infrastructure where all the necessary pieces are easily available to those who wish to do research on EDA algorithms and flows.  So by openly available we mean (a) the source code is freely available, along with make files and some examples with known results, all capable of running on a stock Linux system, and (b) the licensing terms, if any, are appropriate for research.  

Note that (b) applies not only to the global router itself, but any code it requires.  For example, if your global router needs a SAT solver from another group, the SAT solver must in turn be easily available for research for your entry to qualify.  IEEE/CEDA will test (a) and be the final judge of (b) before awarding the prize.


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