ISPD 2010 Clock Network Synthesis contest

This file explains the input/output file format by examples.

//--------------------------------------------------------------------------//
//--------------------------------------------------------------------------//
input file

0 0 5000000 5000000      // lower_left_x,y upper_right_x,y (in nm) = 0.5cm x 0.5cm
source 0 0 0 0           // source sourceName x y bufName
num sink 7              
1 1200000 1300000 35     // sinkName x y load_cap(in fF)
2 4000000 1200000 35
3 1300000 3800000 35
4 3700000 3300000 35
5 3700000 3450000 35
6 3800000 3650000 35
7 3750000 3850000 35
num wirelib 2
0 0.0001 0.0002          // wireTypeName unit_wire_resistance (Ohm/nm) unit_wire_capacitance (fF/nm)
1 0.0003 0.00016
num buflib 2
0 clkinv0.subckt 1 35 80 61.2 // buf_id spice_subckt_filename inverted? input_load_cap output_parasitic_cap output_resistance
1 clkinv1.subckt 1 4.2 6.1 440
nominal vdd 1.0               // nominal vdd for spice simulation 
variation vdd 0.15            // 15% of vdd variation
variation wire 0.1            // 10% of wire variation
limit slew 100                // slew limit in ps
limit localskew 5.999         // local skew limit in ps
localskew distance 600000     // sink distance constraint for local skew calculation
num simulation 10
num blockage 4
1000 1000 1000000 2800000 // lower_left_x,y upper_right_x,y (in nm)
1000 3000000 1800000 3400000
1000 3500000 1000000 4800000
2100000 2800000 3500000 4800000

===============
Notes:
spice_subckt_filename "clkinv0.subckt" must exist in current directory
spice_subckt_filename "clkinv1.subckt" must exist in current directory

//--------------------------------------------------------------------------//
//--------------------------------------------------------------------------//
output file

sourcenode 0 0   // nodeName srcName(must_be_the_same_as_the_source_name_in_input_file)
num node 21
1  1250000 0     // nodeName x y
2  1250000 0
3  2500000 0
4  2500000 0
5  2500000 1250000
6  2500000 1250000
7  2500000 2500000
8  2500000 2500000
9  2500000 2500000
10 2500000 2500000
11 2500000 2500000
12 2500000 2500000
13 1250000 2480000
14 1250000 2480000
15 1250000 2480000
16 1250000 2480000
17 1250000 2480000
18 1250000 2480000
19 3750000 2480000
20 3750000 2480000
21 1250000 3000000
num sinknode 4
25 1             // nodeName sinkName(must_be_the_same_as_one_of_sink_names_in_input_file)
26 3
27 2
28 4
num wire 20
0 1 0            // from_nodeName to_nodeName wireType(must_be_the_same_as_one_of_the_wire_type_in_input_file)
2 3 0
4 5 0
6 7 0
7 8 0
7 9 0
10 12 0
11 12 0
12 13 0
13 14 0
13 15 0
17 18 0
16 18 0
18 25 0
18 21 0          // two nodes can be connected by more than one wire
18 21 0          //
21 26 0
12 19 0
20 27 0
20 28 1
num buffer 9
1 2 0            // from_nodeName to_nodeName bufType(must_be_the_same_as_one_of_the_buf_type_in_input_file)
3 4 0
5 6 0
8 10 0
9 11 0
14 16 0
15 17 0
19 20 0          // two nodes can be connected by more than one buffer
19 20 0          //

===============
Notes:
For buffers, the from_nodeName and to_nodeName must have same x,y location.