--------------------------------------------------------------------- Q. Is wire snaking allowed? A. Yes, wire snaking is allowed. --------------------------------------------------------------------- Q. Are the values of the capacitance on the sinks going to vary in the test designs? I saw the example as 35fF. A. Yes, the sink capacitance may vary. --------------------------------------------------------------------- Q. Does the internal node coordinate assign floating point? ex: num node 2 1 12.1 13.6 2 10.5 20.3 A. Yes, floating point can be used. --------------------------------------------------------------------- Q. Does any sink locate on the blockage area or blockage boundary? ex: num sink 2 1 10 10 35 2 20 20 35 num blockage 1 0 0 20 20 A. Yes, a pin can be inside a blockage. However, since we have slew constraints, I am sure the distance from any "in-blockage" pin to the blockage boundary would be not be large. --------------------------------------------------------------------- Q. You mentioned that the process variation will be modeled by varying the supply voltage. Do we need to perform, for example, decap insertion to improve our clock networks? As far as I know, decap insertion is to prevent power supply noise. But this seems different from the supply voltage change mentioned in the contest webpage. A. In this contest, we focus on the effect of voltage variation on clock arrival time (i.e. delay). We don't care about power supply noise. So, you don't have to do decap insertion in this contest. I highly recommend you try my script eval2009.pl for s1 and s1s. And set "-v 1", then you will be able to see what out objectives are... --------------------------------------------------------------------- Q. Can I insert buffer at blockage boundary? for example: blockage at 1 1 10 10 , buffer at 1 5. A. No, placing the buffer on the blockage boundary is not allowed. However, you can put the buffer at 0.9999 5. --------------------------------------------------------------------- Q. Can we use multi-core programming? A. You can use multiple CPU parallel computing. You can use up to 4 CPU. However, CPU time of your clock network synthesis binary is not the key objective of the contest. --------------------------------------------------------------------- Q. I like to know if you can tell us the model for the delay of buffer, which used by ngspice. Or some parameter like the output resistance of buffer, and intrinsic delay of buffer? A. This is one of the challenges of the contest. I can tell you clkinv0.subckt has output resistance of 61.2 Ohm. However, it is just an estimation (I changed the output loading capacitance and get the delay. Then the slope of the curve is the resistance.) And, I did not calculate the intrinsic delay by myself. It is very easy (hint: change the output loading capacitance) and you can surely do it yourself. On the other hand, I don't think you should manually get the buffer input cap, output res, intrinsic delay because 1) you may have a different inverter given in the real benchmarks for the ranking purpose. 2) using these number and calculate the RC delay is very inaccurate (if your goal is to make the CLR to be less than 10ps) 3) the numbers will be different if I apply different voltage to the inverter. Delay along the inverter will change a lot upon supply voltage variation. If you use these three number inside your algorithm, I am sure your CLR will be big. --------------------------------------------------------------------- Q. Does the wires have to be horizontal or vertical? From the sample output s1s, it seems that they have to but I want to make sure. A. No. it doesn't have to be horizontal or vertical. However, all distance will be calculated in Manhattan distance, which is abs(x2-x1) + abs(y2-y1). So, a diagonal wire is effectively the same as horizontal+vertical wires. --------------------------------------------------------------------- Q. While working with the sample clock tree s1s we have realized that the wires are not necessarily horizontal or vertical, it can run in any direction, is that correct? Lets say I want to connect nodes 12 and 13 12 2500000 2500000 13 1250000 2480000 can I add a single wire ? 12 13 0 A. Right. You are connect 12 to 13 directly! --------------------------------------------------------------------- Q. Can you say whether the buffer library and interconnect widths / RC's are going to change in the "real contest", as opposed in the samples currently on the web? A. I think we will keep the clkinv0.subckt but we may add a couple buffers/inverters in different benchmarks. --------------------------------------------------------------------- Q. Will the organizers' processing script (that takes the contestant's output and feeds to SPICE) remain the same as what is currently on the web? A. It will be similar. However, there will be some bug fixes and new features, such as blockage checking, long interconnect segmentation and better ngspice output reading. --------------------------------------------------------------------- Q. If a connection must be embedded as an "L", it seems that your script will segment it into one "H" segment and one "V" segment. Will this be done for the contest exactly as done in your script that is currently on the web? A. I don't think I segment a "L" interconnect into a "H" and "V", in the current eval2009.pl. Can you please explain this question in more detail? Are you talking about my using Manhattan distance instead of Euclidean? I believe Manhattan distance is more reasonable in this case. By the way, I am going to add a long interconnect segmentation step before Pi-model translation to account for the Ceff issue. So, any long interconnect will be segment no matter a "L" or a straight line. --------------------------------------------------------------------- Q. Will the contest results be evaluated with the HSPICE tool, or NGSPICE, or something else? We would like to understand this since your answer may have implications for the complexity of the contest problem instances as well as the strategies we use for generating outputs. A. We will use ngspice for sure. I will just run eval2009.pl to get the CLR of your solution. --------------------------------------------------------------------- Q. Our group is discussing with some details of CTS these days, now that there're two types of wire and one type of buffer published in your official website, we just wonder whether more than one type of buffer will get involved finally ? Thank you ! A. Yes. I believe we will get one more type of buffers/inverters. --------------------------------------------------------------------- Q. I still have a few questions about the process variation part. To the best of my knowledge, varying the supply voltage only affects the delay of the buffers, but not the interconnects. Is that correct? In my previous research on process variation, I treated the unit resistance and capacitance of the interconnects as random variables, and that made the interconnect delays also random variables. So we are not going to consider the interconnect variation due to process variation in this contest. Is that correct? Another thing is that I was told that you will be providing BC and WC parameters to model the process variation. I did some searches but I'm not really sure what these parameters are. Could you please clarify this to me? A. Yes. The supply voltage affects the inverter delay much much more than interconnects. And right, in this contest, we are NOT considering interconnect variation. No, there will be no BC/WC values. We only focus on delay variation when inverter supply voltage varies. --------------------------------------------------------------------- Q. There is no output resistance information in buffer library. With only input loading capacitance and output parasitic capacitance, it is not available to be applied to the Elmore delay. Is it possible that the benchmark provides the output resistance information of buffers? A. Sure. I can tell you the output resistance of "clkinv0.subckt" in the sample testcase is 61.2 Ohm, The line in s1 will become 0 clkinv0.subckt 1 35 80 61.2 However, I must warn you 1) the output resistance value is calculated based on a few spice simulation with different cap loading. So using it with Elmore model will have errors. 2) Since I will only provide the output resistance in single voltage (e.g. 1V), you have to think about how to scale the output resistance for different voltages. --------------------------------------------------------------------- Q. About "simulation vdd" format of input file, does "simulation vdd 1 1.2" means there are two simulation vdd at 1 volt and 1.2 volt? Or, it means that there is "one" simulation vdd, 1.2 volt? A. "simulation vdd 1 1.2" means there are two simulation vdd at 1 volt and 1.2 volt --------------------------------------------------------------------- Q. Does every two blockages always has non-zero distance? In other words, could we assume that there is no two blockages having boundary overlap? A. I will overlap blockages and create special shaped blockages such as "L" shape blockages, etc.... --------------------------------------------------------------------- Q. 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