* spice circuit for a clock inverter
.include tuned_45nm_HP.pm
.subckt inv in out vdd
m1  out in  vdd vdd   pmos l=45n w=14.6u
m2  out in  0   0     nmos l=45n w=10.0u 
.ends inv
*
x1 gin gout vdd inv
cLoad gout 0 0.5p
*
vdd vdd 0 1.0
vdt gin 0 1.0 pwl(0n 0.0, 0.25n 0.0, 0.35n 1.0, 0.50n 1.0, 0.60n 0.0, 3n 0.0)
*
.ic v(gin)=0.0
.ic v(gout)=1.0
*
.opti nopage temp=50
.width out=240
*
.tran 0.005n 3n 0.0n 0.005n
.print tran v(gout)
.end